3e84da55a6
Added msp432 flash driver to support the TI MSP432P4x and MSP432E4x microcontrollers. Implemented the flash algo helper as used in the TI debug and flash tools. This implemention supports the MSP432E4, Falcon, and Falcon 2M variants. The flash driver automatically detects the connected variant and configures itself appropriately. Added command to mass erase device for consistency with TI tools and added command to unlock the protected BSL region. Tested using MSP432E401Y, MSP432P401R, and MSP432P4111 LaunchPads. Tested with embedded XDS110 debug probe in CMSIS-DAP mode and with external SEGGER J-Link probe. Removed ti_msp432p4xx.cfg file made obsolete by this patch. Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
230 lines
12 KiB
C
230 lines
12 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
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#define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Register map for FLASH_CTRL peripheral (FLASH_CTRL) */
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struct flash_ctrl {
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volatile uint32_t FMA; /* Flash Memory Address */
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volatile uint32_t FMD; /* Flash Memory Data */
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volatile uint32_t FMC; /* Flash Memory Control */
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volatile uint32_t FCRIS; /* Flash Controller Raw Interrupt Status */
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volatile uint32_t FCIM; /* Flash Controller Interrupt Mask */
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volatile uint32_t FCMISC; /* Flash Cont. Masked Int. Status and Clear */
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volatile uint32_t RESERVED0[2];
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volatile uint32_t FMC2; /* Flash Memory Control 2 */
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volatile uint32_t RESERVED1[3];
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volatile uint32_t FWBVAL; /* Flash Write Buffer Valid */
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volatile uint32_t RESERVED2[2];
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volatile uint32_t FLPEKEY; /* Flash Program/Erase Key */
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volatile uint32_t RESERVED3[48];
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volatile uint32_t FWBN[32]; /* Flash Write Buffer n */
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};
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/* Register map for SYSCTL peripheral (SYSCTL) */
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struct sys_ctrl {
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volatile uint32_t DID0; /* Device Identification 0 */
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volatile uint32_t DID1; /* Device Identification 1 */
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volatile uint32_t RESERVED0[12];
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volatile uint32_t PTBOCTL; /* Power-Temp Brown Out Control */
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volatile uint32_t RESERVED1[5];
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volatile uint32_t RIS; /* Raw Interrupt Status */
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volatile uint32_t IMC; /* Interrupt Mask Control */
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volatile uint32_t MISC; /* Masked Interrupt Status and Clear */
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volatile uint32_t RESC; /* Reset Cause */
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volatile uint32_t PWRTC; /* Power-Temperature Cause */
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volatile uint32_t NMIC; /* NMI Cause Register */
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volatile uint32_t RESERVED2[5];
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volatile uint32_t MOSCCTL; /* Main Oscillator Control */
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volatile uint32_t RESERVED3[12];
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volatile uint32_t RSCLKCFG; /* Run and Sleep Mode Configuration Register */
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volatile uint32_t RESERVED4[3];
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volatile uint32_t MEMTIM0; /* Memory Timing Register 0 for Main Flash */
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volatile uint32_t RESERVED5[29];
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volatile uint32_t ALTCLKCFG; /* Alternate Clock Configuration */
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volatile uint32_t RESERVED6[2];
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union {
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volatile uint32_t DSLPCLKCFG; /* Deep Sleep Clock Configuration */
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volatile uint32_t DSCLKCFG; /* Deep Sleep Clock Register */
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};
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volatile uint32_t DIVSCLK; /* Divisor and Source Clock Configuration */
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volatile uint32_t SYSPROP; /* System Properties */
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volatile uint32_t PIOSCCAL; /* Precision Internal Oscillator Calibration */
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volatile uint32_t PIOSCSTAT; /* Precision Internal Oscillator Statistics */
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volatile uint32_t RESERVED7[2];
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volatile uint32_t PLLFREQ0; /* PLL Frequency 0 */
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volatile uint32_t PLLFREQ1; /* PLL Frequency 1 */
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volatile uint32_t PLLSTAT; /* PLL Status */
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volatile uint32_t RESERVED8[7];
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volatile uint32_t SLPPWRCFG; /* Sleep Power Configuration */
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volatile uint32_t DSLPPWRCFG; /* Deep-Sleep Power Configuration */
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volatile uint32_t RESERVED9[4];
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volatile uint32_t NVMSTAT; /* Non-Volatile Memory Information */
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volatile uint32_t RESERVED10[4];
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volatile uint32_t LDOSPCTL; /* LDO Sleep Power Control */
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volatile uint32_t RESERVED11;
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volatile uint32_t LDODPCTL; /* LDO Deep-Sleep Power Control */
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volatile uint32_t RESERVED12[6];
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volatile uint32_t RESBEHAVCTL; /* Reset Behavior Control Register */
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volatile uint32_t RESERVED13[6];
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volatile uint32_t HSSR; /* Hardware System Service Request */
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volatile uint32_t RESERVED14[34];
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volatile uint32_t USBPDS; /* USB Power Domain Status */
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volatile uint32_t USBMPC; /* USB Memory Power Control */
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volatile uint32_t EMACPDS; /* Ethernet MAC Power Domain Status */
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volatile uint32_t EMACMPC; /* Ethernet MAC Memory Power Control */
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volatile uint32_t RESERVED15;
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volatile uint32_t LCDMPC; /* LCD Memory Power Control */
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volatile uint32_t RESERVED16[26];
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volatile uint32_t PPWD; /* Watchdog Timer Peripheral Present */
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volatile uint32_t PPTIMER; /* General-Purpose Timer Peripheral Present */
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volatile uint32_t PPGPIO; /* General-Purpose I/O Peripheral Present */
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volatile uint32_t PPDMA; /* Micro DMA Peripheral Present */
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volatile uint32_t PPEPI; /* EPI Peripheral Present */
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volatile uint32_t PPHIB; /* Hibernation Peripheral Present */
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volatile uint32_t PPUART; /* UART Peripheral Present */
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volatile uint32_t PPSSI; /* Synchronous Serial Inter. Periph. Present */
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volatile uint32_t PPI2C; /* Inter-Integrated Circuit Periph. Present */
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volatile uint32_t RESERVED17;
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volatile uint32_t PPUSB; /* Universal Serial Bus Peripheral Present */
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volatile uint32_t RESERVED18;
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volatile uint32_t PPEPHY; /* Ethernet PHY Peripheral Present */
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volatile uint32_t PPCAN; /* Controller Area Network Periph. Present */
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volatile uint32_t PPADC; /* Analog-to-Dig. Converter Periph. Present */
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volatile uint32_t PPACMP; /* Analog Comparator Peripheral Present */
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volatile uint32_t PPPWM; /* Pulse Width Modulator Peripheral Present */
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volatile uint32_t PPQEI; /* Quadrature Encoder Inter. Periph. Present */
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volatile uint32_t RESERVED19[4];
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volatile uint32_t PPEEPROM; /* EEPROM Peripheral Present */
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volatile uint32_t RESERVED20[6];
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volatile uint32_t PPCCM; /* CRC/Cryptographic Modules Periph. Present */
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volatile uint32_t RESERVED21[6];
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volatile uint32_t PPLCD; /* LCD Peripheral Present */
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volatile uint32_t RESERVED22;
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volatile uint32_t PPOWIRE; /* 1-Wire Peripheral Present */
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volatile uint32_t PPEMAC; /* Ethernet MAC Peripheral Present */
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volatile uint32_t RESERVED23[88];
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volatile uint32_t SRWD; /* Watchdog Timer Software Reset */
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volatile uint32_t SRTIMER; /* General-Purpose Timer Software Reset */
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volatile uint32_t SRGPIO; /* General-Purpose I/O Software Reset */
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volatile uint32_t SRDMA; /* Micro Direct Memory Access Software Reset */
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volatile uint32_t SREPI; /* EPI Software Reset */
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volatile uint32_t SRHIB; /* Hibernation Software Reset */
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volatile uint32_t SRUART; /* UART Software Reset */
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volatile uint32_t SRSSI; /* Synchronous Serial Inter. Software Reset */
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volatile uint32_t SRI2C; /* Inter-Integrated Circuit Software Reset */
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volatile uint32_t RESERVED24;
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volatile uint32_t SRUSB; /* Universal Serial Bus Software Reset */
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volatile uint32_t RESERVED25;
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volatile uint32_t SREPHY; /* Ethernet PHY Software Reset */
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volatile uint32_t SRCAN; /* Controller Area Network Software Reset */
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volatile uint32_t SRADC; /* Analog-to-Dig. Converter Software Reset */
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volatile uint32_t SRACMP; /* Analog Comparator Software Reset */
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volatile uint32_t SRPWM; /* Pulse Width Modulator Software Reset */
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volatile uint32_t SRQEI; /* Quadrature Encoder Inter. Software Reset */
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volatile uint32_t RESERVED26[4];
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volatile uint32_t SREEPROM; /* EEPROM Software Reset */
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volatile uint32_t RESERVED27[6];
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volatile uint32_t SRCCM; /* CRC/Cryptographic Modules Software Reset */
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volatile uint32_t RESERVED28[6];
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volatile uint32_t SRLCD; /* LCD Controller Software Reset */
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volatile uint32_t RESERVED29;
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volatile uint32_t SROWIRE; /* 1-Wire Software Reset */
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volatile uint32_t SREMAC; /* Ethernet MAC Software Reset */
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volatile uint32_t RESERVED30[24];
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volatile uint32_t RCGCWD; /* Watchdog Run Mode Clock Gating Control */
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};
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/* Peripheral Memory Map */
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#define FLASH_CTRL_BASE 0x400FD000UL
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#define SYSCTL_BASE 0x400FE000UL
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/* Peripheral Declarations */
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#define FLASH_CTRL ((struct flash_ctrl *) FLASH_CTRL_BASE)
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#define SYSCTL ((struct sys_ctrl *) SYSCTL_BASE)
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/* The following are defines for the bit fields in the FLASH_FMC register. */
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#define FLASH_FMC_WRKEY 0xA4420000 /* FLASH write key */
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#define FLASH_FMC_COMT 0x00000008 /* Commit Register Value */
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#define FLASH_FMC_MERASE 0x00000004 /* Mass Erase Flash Memory */
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#define FLASH_FMC_ERASE 0x00000002 /* Erase a Page of Flash Memory */
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#define FLASH_FMC_WRITE 0x00000001 /* Write a Word into Flash Memory */
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/* The following are defines for the bit fields in the FLASH_FCRIS register. */
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#define FLASH_FCRIS_PROGRIS 0x00002000 /* Program Verify Raw Interrupt Status */
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#define FLASH_FCRIS_ERRIS 0x00000800 /* Erase Verify Raw Interrupt Status */
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#define FLASH_FCRIS_INVDRIS 0x00000400 /* Invalid Data Raw Interrupt Status */
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#define FLASH_FCRIS_VOLTRIS 0x00000200 /* Pump Voltage Raw Interrupt Status */
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#define FLASH_FCRIS_ERIS 0x00000004 /* EEPROM Raw Interrupt Status */
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#define FLASH_FCRIS_PRIS 0x00000002 /* Programming Raw Interrupt Status */
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#define FLASH_FCRIS_ARIS 0x00000001 /* Access Raw Interrupt Status */
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/* The following are defines for the bit fields in the FLASH_FCIM register. */
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#define FLASH_FCIM_PROGMASK 0x00002000 /* PROGVER Interrupt Mask */
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#define FLASH_FCIM_ERMASK 0x00000800 /* ERVER Interrupt Mask */
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#define FLASH_FCIM_INVDMASK 0x00000400 /* Invalid Data Interrupt Mask */
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#define FLASH_FCIM_VOLTMASK 0x00000200 /* VOLT Interrupt Mask */
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#define FLASH_FCIM_EMASK 0x00000004 /* EEPROM Interrupt Mask */
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#define FLASH_FCIM_PMASK 0x00000002 /* Programming Interrupt Mask */
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#define FLASH_FCIM_AMASK 0x00000001 /* Access Interrupt Mask */
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/* The following are defines for the bit fields in the FLASH_FCMISC register. */
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#define FLASH_FCMISC_PROGMISC 0x00002000 /* PROGVER Interrupt Status/Clear */
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#define FLASH_FCMISC_ERMISC 0x00000800 /* ERVER Interrupt Status/Clear */
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#define FLASH_FCMISC_INVDMISC 0x00000400 /* Invalid Data Int. Status/Clear */
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#define FLASH_FCMISC_VOLTMISC 0x00000200 /* VOLT Interrupt Status/Clear */
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#define FLASH_FCMISC_EMISC 0x00000004 /* EEPROM Interrupt Status/Clear */
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#define FLASH_FCMISC_PMISC 0x00000002 /* Programming Int. Status/Clear */
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#define FLASH_FCMISC_AMISC 0x00000001 /* Access Interrupt Status/Clear */
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/* The following are defines for the bit fields in the FLASH_FMC2 register. */
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#define FLASH_FMC2_WRBUF 0x00000001 /* Buffered Flash Memory Write */
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/* The following are defines for the bit fields in the SYSCTL_RCGCWD reg. */
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#define SYSCTL_RCGCWD_R1 0x00000002 /* Watchdog 1 Run Mode Clock Gating Cont. */
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#define SYSCTL_RCGCWD_R0 0x00000001 /* Watchdog 0 Run Mode Clock Gating Cont. */
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#ifdef __cplusplus
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}
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#endif
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#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H */
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