158 lines
4.7 KiB
C
158 lines
4.7 KiB
C
/***************************************************************************
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* Copyright (C) 2008 digenius technology GmbH. *
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* Michael Bruck *
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* *
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* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM11_H
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#define ARM11_H
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#include "armv4_5.h"
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#include "arm_dpm.h"
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#define ARM11_REGCACHE_COUNT 3
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#define ARM11_TAP_DEFAULT TAP_INVALID
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#define CHECK_RETVAL(action) \
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do { \
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int __retval = (action); \
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if (__retval != ERROR_OK) { \
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LOG_DEBUG("error while calling \"%s\"", \
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# action ); \
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return __retval; \
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} \
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} while (0)
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enum arm11_debug_version
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{
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ARM11_DEBUG_V6 = 0x01,
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ARM11_DEBUG_V61 = 0x02,
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ARM11_DEBUG_V7 = 0x03,
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ARM11_DEBUG_V7_CP14 = 0x04,
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};
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struct arm11_common
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{
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struct arm arm;
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struct target * target; /**< Reference back to the owner */
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/** Debug module state. */
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struct arm_dpm dpm;
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/** \name Processor type detection */
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/*@{*/
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size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
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size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
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/*@}*/
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uint32_t last_dscr; /**< Last retrieved DSCR value;
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Use only for debug message generation */
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bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
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/** \name Shadow registers to save debug state */
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/*@{*/
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struct reg * reg_list; /**< target register list */
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uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
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/*@}*/
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size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
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size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
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// GA
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struct reg_cache *core_cache;
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struct arm_jtag jtag_info;
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};
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static inline struct arm11_common *target_to_arm11(struct target *target)
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{
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return container_of(target->arch_info, struct arm11_common,
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arm);
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}
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/**
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* ARM11 DBGTAP instructions
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*
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* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
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*/
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enum arm11_instructions
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{
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ARM11_EXTEST = 0x00,
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ARM11_SCAN_N = 0x02,
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ARM11_RESTART = 0x04,
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ARM11_HALT = 0x08,
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ARM11_INTEST = 0x0C,
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ARM11_ITRSEL = 0x1D,
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ARM11_IDCODE = 0x1E,
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ARM11_BYPASS = 0x1F,
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};
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enum arm11_dscr
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{
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ARM11_DSCR_CORE_HALTED = 1 << 0,
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ARM11_DSCR_CORE_RESTARTED = 1 << 1,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
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ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
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ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
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ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
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ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
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ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
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ARM11_DSCR_MODE_SELECT = 1 << 14,
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ARM11_DSCR_WDTR_FULL = 1 << 29,
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ARM11_DSCR_RDTR_FULL = 1 << 30,
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};
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enum arm11_cpsr
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{
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ARM11_CPSR_T = 1 << 5,
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ARM11_CPSR_J = 1 << 24,
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};
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enum arm11_sc7
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{
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ARM11_SC7_NULL = 0,
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ARM11_SC7_VCR = 7,
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ARM11_SC7_PC = 8,
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ARM11_SC7_BVR0 = 64,
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ARM11_SC7_BCR0 = 80,
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ARM11_SC7_WVR0 = 96,
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ARM11_SC7_WCR0 = 112,
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};
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struct arm11_reg_state
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{
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uint32_t def_index;
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struct target * target;
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};
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#endif /* ARM11_H */
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