386155419b
While reviewing on gerrit the change https://review.openocd.org/6932/ it get clear that the missing documentation on stm32f4x's code was triggering errors in the new change. OpenOCD is currently unable to read traces, but these can be hopefully be read with some other tool. Document the settings for enabling trace on stm32[fl]4x. Change-Id: Ibae77a53de16375d3d500e728678740095547009 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6945 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
157 lines
4.5 KiB
INI
157 lines
4.5 KiB
INI
# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32l4x family
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#
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# stm32l4 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 40kB (Available RAM in smallest device STM32L412)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0xa000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0351
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# Section 44.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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} else {
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if { [info exists OCTOSPI1] && $OCTOSPI1 } {
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set a [llength [flash list]]
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set _OCTOSPINAME1 $_CHIPNAME.octospi1
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flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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if { [info exists OCTOSPI2] && $OCTOSPI2 } {
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set b [llength [flash list]]
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set _OCTOSPINAME2 $_CHIPNAME.octospi2
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flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
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}
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}
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {
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targets $_chipname.cpu
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if { [$_chipname.tpiu cget -protocol] eq "sync" } {
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switch [$_chipname.tpiu cget -port-width] {
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1 {
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# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0
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mmw 0xE0042004 0x00000060 0x000000c0
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mmw 0x48001020 0x00000000 0x0000ff00
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mmw 0x48001000 0x000000a0 0x000000f0
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mmw 0x48001008 0x000000f0 0x00000000
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}
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2 {
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# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0
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mmw 0xE0042004 0x000000a0 0x000000c0
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mmw 0x48001020 0x00000000 0x000fff00
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mmw 0x48001000 0x000002a0 0x000003f0
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mmw 0x48001008 0x000003f0 0x00000000
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}
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4 {
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# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0
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mmw 0xE0042004 0x000000e0 0x000000c0
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mmw 0x48001020 0x00000000 0x0fffff00
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mmw 0x48001000 0x00002aa0 0x00003ff0
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mmw 0x48001008 0x00003ff0 0x00000000
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}
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}
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} else {
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# Set TRACE_IOEN; TRACE_MODE to async
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mmw 0xE0042004 0x00000020 0x000000c0
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}
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME"
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
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# Use MSI 24 MHz clock, compliant even with VOS == 2.
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# 3 WS compliant with VOS == 2 and 24 MHz.
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mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
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mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 500
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}
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