b2821b6074
With this commit we add tcl configure files for ARCv2 HS Development kit(HSDK). HSDK board has Quad-core ARC HS38 CPU with L1 and L2 caches. Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0 Signed-off-by: Evgeniy Didin <didin@synopsys.com> Reviewed-on: http://openocd.zylin.com/5784 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
87 lines
2.5 KiB
INI
87 lines
2.5 KiB
INI
# Copyright (C) 2019,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr ($_coreid << 13)]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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# ARC HS38 core 4
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set _TARGETNAME $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 3
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set _TARGETNAME $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 2
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set _TARGETNAME $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 1
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set _TARGETNAME $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME arc cache l2 auto 1
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