698 lines
17 KiB
C
698 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (c) 2019 Google, LLC.
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* Author: Moritz Fischer <moritzf@google.com>
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <stdint.h>
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#include <stdlib.h>
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#include <math.h>
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#include <unistd.h>
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#include <linux/pci.h>
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#include <jtag/interface.h>
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#include <jtag/swd.h>
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#include <jtag/commands.h>
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#include <helper/replacements.h>
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#include <helper/bits.h>
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/* Available only from kernel v4.10 */
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#ifndef PCI_CFG_SPACE_EXP_SIZE
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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#endif
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#define PCIE_EXT_CAP_LST 0x100
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#define XLNX_XVC_EXT_CAP 0x00
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#define XLNX_XVC_VSEC_HDR 0x04
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#define XLNX_XVC_LEN_REG 0x0C
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#define XLNX_XVC_TMS_REG 0x10
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#define XLNX_XVC_TDx_REG 0x14
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#define XLNX_XVC_CAP_SIZE 0x20
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#define XLNX_XVC_VSEC_ID 0x8
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#define XLNX_XVC_MAX_BITS 0x20
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#define MASK_ACK(x) (((x) >> 9) & 0x7)
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#define MASK_PAR(x) ((int)((x) & 0x1))
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struct xlnx_pcie_xvc {
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int fd;
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unsigned offset;
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char *device;
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};
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static struct xlnx_pcie_xvc xlnx_pcie_xvc_state;
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static struct xlnx_pcie_xvc *xlnx_pcie_xvc = &xlnx_pcie_xvc_state;
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static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
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{
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uint32_t res;
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int err;
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/* Note: This should be ok endianness-wise because by going
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* through sysfs the kernel does the conversion in the config
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* space accessor functions
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*/
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err = pread(xlnx_pcie_xvc->fd, &res, sizeof(res),
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xlnx_pcie_xvc->offset + offset);
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if (err != sizeof(res)) {
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LOG_ERROR("Failed to read offset %x", offset);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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if (val)
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*val = res;
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
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{
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int err;
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/* Note: This should be ok endianness-wise because by going
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* through sysfs the kernel does the conversion in the config
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* space accessor functions
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*/
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err = pwrite(xlnx_pcie_xvc->fd, &val, sizeof(val),
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xlnx_pcie_xvc->offset + offset);
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if (err != sizeof(val)) {
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LOG_ERROR("Failed to write offset: %x with value: %x",
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offset, val);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
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uint32_t *tdo)
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{
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int err;
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err = xlnx_pcie_xvc_write_reg(XLNX_XVC_LEN_REG, num_bits);
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if (err != ERROR_OK)
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return err;
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err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TMS_REG, tms);
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if (err != ERROR_OK)
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return err;
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err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TDx_REG, tdi);
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if (err != ERROR_OK)
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return err;
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err = xlnx_pcie_xvc_read_reg(XLNX_XVC_TDx_REG, tdo);
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if (err != ERROR_OK)
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return err;
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if (tdo)
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LOG_DEBUG_IO("Transact num_bits: %zu, tms: %x, tdi: %x, tdo: %x",
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num_bits, tms, tdi, *tdo);
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else
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LOG_DEBUG_IO("Transact num_bits: %zu, tms: %x, tdi: %x, tdo: <null>",
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num_bits, tms, tdi);
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return ERROR_OK;
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}
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int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
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{
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int tms = tap_get_state() == TAP_RESET ? 1 : 0;
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size_t left = cmd->cmd.stableclocks->num_cycles;
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size_t write;
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int err;
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LOG_DEBUG("stableclocks %i cycles", cmd->cmd.runtest->num_cycles);
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while (left) {
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write = MIN(XLNX_XVC_MAX_BITS, left);
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err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
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if (err != ERROR_OK)
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return err;
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left -= write;
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};
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_execute_statemove(size_t skip)
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{
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uint8_t tms_scan = tap_get_tms_path(tap_get_state(),
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tap_get_end_state());
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int tms_count = tap_get_tms_path_len(tap_get_state(),
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tap_get_end_state());
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int err;
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LOG_DEBUG("statemove starting at (skip: %zu) %s end in %s", skip,
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tap_state_name(tap_get_state()),
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tap_state_name(tap_get_end_state()));
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err = xlnx_pcie_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL);
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if (err != ERROR_OK)
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return err;
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tap_set_state(tap_get_end_state());
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
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{
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int err = ERROR_OK;
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LOG_DEBUG("runtest %i cycles, end in %i",
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cmd->cmd.runtest->num_cycles,
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cmd->cmd.runtest->end_state);
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tap_state_t tmp_state = tap_get_end_state();
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if (tap_get_state() != TAP_IDLE) {
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tap_set_end_state(TAP_IDLE);
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err = xlnx_pcie_xvc_execute_statemove(0);
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if (err != ERROR_OK)
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return err;
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};
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size_t left = cmd->cmd.runtest->num_cycles;
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size_t write;
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while (left) {
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write = MIN(XLNX_XVC_MAX_BITS, left);
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err = xlnx_pcie_xvc_transact(write, 0, 0, NULL);
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if (err != ERROR_OK)
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return err;
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left -= write;
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};
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tap_set_end_state(tmp_state);
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if (tap_get_state() != tap_get_end_state())
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err = xlnx_pcie_xvc_execute_statemove(0);
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return err;
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}
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static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
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{
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size_t num_states = cmd->cmd.pathmove->num_states;
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tap_state_t *path = cmd->cmd.pathmove->path;
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int err = ERROR_OK;
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size_t i;
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LOG_DEBUG("pathmove: %i states, end in %i",
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cmd->cmd.pathmove->num_states,
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cmd->cmd.pathmove->path[cmd->cmd.pathmove->num_states - 1]);
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for (i = 0; i < num_states; i++) {
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if (path[i] == tap_state_transition(tap_get_state(), false)) {
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err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
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} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
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err = xlnx_pcie_xvc_transact(1, 0, 0, NULL);
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} else {
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LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
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tap_state_name(tap_get_state()),
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tap_state_name(path[i]));
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err = ERROR_JTAG_QUEUE_FAILED;
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}
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if (err != ERROR_OK)
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return err;
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tap_set_state(path[i]);
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}
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tap_set_end_state(tap_get_state());
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
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{
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enum scan_type type = jtag_scan_type(cmd->cmd.scan);
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tap_state_t saved_end_state = cmd->cmd.scan->end_state;
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bool ir_scan = cmd->cmd.scan->ir_scan;
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uint32_t tdi, tms, tdo;
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uint8_t *buf, *rd_ptr;
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int err, scan_size;
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size_t write;
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size_t left;
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scan_size = jtag_build_buffer(cmd->cmd.scan, &buf);
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rd_ptr = buf;
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LOG_DEBUG("%s scan type %d %d bits; starts in %s end in %s",
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(cmd->cmd.scan->ir_scan) ? "IR" : "DR", type, scan_size,
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tap_state_name(tap_get_state()),
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tap_state_name(cmd->cmd.scan->end_state));
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/* If we're in TAP_DR_SHIFT state but need to do a IR_SCAN or
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* vice-versa, do a statemove to corresponding other state, then restore
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* end state
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*/
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if (ir_scan && tap_get_state() != TAP_IRSHIFT) {
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tap_set_end_state(TAP_IRSHIFT);
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err = xlnx_pcie_xvc_execute_statemove(0);
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if (err != ERROR_OK)
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goto out_err;
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tap_set_end_state(saved_end_state);
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} else if (!ir_scan && (tap_get_state() != TAP_DRSHIFT)) {
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tap_set_end_state(TAP_DRSHIFT);
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err = xlnx_pcie_xvc_execute_statemove(0);
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if (err != ERROR_OK)
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goto out_err;
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tap_set_end_state(saved_end_state);
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}
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left = scan_size;
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while (left) {
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write = MIN(XLNX_XVC_MAX_BITS, left);
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/* the last TMS should be a 1, to leave the state */
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tms = left <= XLNX_XVC_MAX_BITS ? BIT(write - 1) : 0;
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tdi = (type != SCAN_IN) ? buf_get_u32(rd_ptr, 0, write) : 0;
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err = xlnx_pcie_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
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&tdo : NULL);
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if (err != ERROR_OK)
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goto out_err;
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left -= write;
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if (type != SCAN_OUT)
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buf_set_u32(rd_ptr, 0, write, tdo);
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rd_ptr += sizeof(uint32_t);
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};
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err = jtag_read_buffer(buf, cmd->cmd.scan);
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if (buf)
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free(buf);
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if (tap_get_state() != tap_get_end_state())
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err = xlnx_pcie_xvc_execute_statemove(1);
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return err;
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out_err:
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if (buf)
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free(buf);
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return err;
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}
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static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)
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{
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LOG_DEBUG("reset trst: %i srst: %i", cmd->cmd.reset->trst,
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cmd->cmd.reset->srst);
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}
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static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)
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{
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LOG_DEBUG("sleep %" PRIi32 "", cmd->cmd.sleep->us);
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usleep(cmd->cmd.sleep->us);
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}
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static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
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{
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const size_t num_bits = cmd->cmd.tms->num_bits;
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const uint8_t *bits = cmd->cmd.tms->bits;
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size_t left, write;
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uint32_t tms;
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int err;
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LOG_DEBUG("execute tms %zu", num_bits);
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left = num_bits;
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while (left) {
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write = MIN(XLNX_XVC_MAX_BITS, left);
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tms = buf_get_u32(bits, 0, write);
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err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
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if (err != ERROR_OK)
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return err;
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left -= write;
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bits += 4;
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};
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
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{
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LOG_DEBUG("%s: cmd->type: %u", __func__, cmd->type);
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switch (cmd->type) {
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case JTAG_STABLECLOCKS:
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return xlnx_pcie_xvc_execute_stableclocks(cmd);
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case JTAG_RUNTEST:
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return xlnx_pcie_xvc_execute_runtest(cmd);
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case JTAG_TLR_RESET:
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tap_set_end_state(cmd->cmd.statemove->end_state);
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return xlnx_pcie_xvc_execute_statemove(0);
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case JTAG_PATHMOVE:
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return xlnx_pcie_xvc_execute_pathmove(cmd);
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case JTAG_SCAN:
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return xlnx_pcie_xvc_execute_scan(cmd);
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case JTAG_RESET:
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xlnx_pcie_xvc_execute_reset(cmd);
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break;
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case JTAG_SLEEP:
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xlnx_pcie_xvc_execute_sleep(cmd);
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break;
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case JTAG_TMS:
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return xlnx_pcie_xvc_execute_tms(cmd);
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default:
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LOG_ERROR("BUG: Unknown JTAG command type encountered.");
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return ERROR_JTAG_QUEUE_FAILED;
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}
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_execute_queue(void)
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{
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struct jtag_command *cmd = jtag_command_queue;
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int ret;
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while (cmd) {
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ret = xlnx_pcie_xvc_execute_command(cmd);
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if (ret != ERROR_OK)
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return ret;
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cmd = cmd->next;
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}
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_init(void)
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{
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char filename[PATH_MAX];
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uint32_t cap, vh;
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int err;
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snprintf(filename, PATH_MAX, "/sys/bus/pci/devices/%s/config",
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xlnx_pcie_xvc->device);
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xlnx_pcie_xvc->fd = open(filename, O_RDWR | O_SYNC);
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if (xlnx_pcie_xvc->fd < 0) {
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LOG_ERROR("Failed to open device: %s", filename);
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return ERROR_JTAG_INIT_FAILED;
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}
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LOG_INFO("Scanning PCIe device %s's for Xilinx XVC/PCIe ...",
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xlnx_pcie_xvc->device);
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/* Parse the PCIe extended capability list and try to find
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* vendor specific header */
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xlnx_pcie_xvc->offset = PCIE_EXT_CAP_LST;
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while (xlnx_pcie_xvc->offset <= PCI_CFG_SPACE_EXP_SIZE - sizeof(cap) &&
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xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
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err = xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, &cap);
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if (err != ERROR_OK)
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return err;
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LOG_DEBUG("Checking capability at 0x%x; id=0x%04x version=0x%x next=0x%x",
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xlnx_pcie_xvc->offset,
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PCI_EXT_CAP_ID(cap),
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PCI_EXT_CAP_VER(cap),
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PCI_EXT_CAP_NEXT(cap));
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if (PCI_EXT_CAP_ID(cap) == PCI_EXT_CAP_ID_VNDR) {
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err = xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR, &vh);
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if (err != ERROR_OK)
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return err;
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LOG_DEBUG("Checking possible match at 0x%x; id: 0x%x; rev: 0x%x; length: 0x%x",
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xlnx_pcie_xvc->offset,
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PCI_VNDR_HEADER_ID(vh),
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PCI_VNDR_HEADER_REV(vh),
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PCI_VNDR_HEADER_LEN(vh));
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if ((PCI_VNDR_HEADER_ID(vh) == XLNX_XVC_VSEC_ID) &&
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(PCI_VNDR_HEADER_LEN(vh) == XLNX_XVC_CAP_SIZE))
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break;
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}
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xlnx_pcie_xvc->offset = PCI_EXT_CAP_NEXT(cap);
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}
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if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||
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xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
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close(xlnx_pcie_xvc->fd);
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return ERROR_JTAG_INIT_FAILED;
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}
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LOG_INFO("Found Xilinx XVC/PCIe capability at offset: 0x%x", xlnx_pcie_xvc->offset);
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return ERROR_OK;
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}
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static int xlnx_pcie_xvc_quit(void)
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{
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int err;
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err = close(xlnx_pcie_xvc->fd);
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if (err)
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return err;
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return ERROR_OK;
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}
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COMMAND_HANDLER(xlnx_pcie_xvc_handle_config_command)
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{
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if (CMD_ARGC < 1)
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return ERROR_COMMAND_SYNTAX_ERROR;
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/* we can't really free this in a safe manner, so at least
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* limit the memory we're leaking by freeing the old one first
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* before allocating a new one ...
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*/
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if (xlnx_pcie_xvc->device)
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free(xlnx_pcie_xvc->device);
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xlnx_pcie_xvc->device = strdup(CMD_ARGV[0]);
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return ERROR_OK;
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}
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static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
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{
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.name = "xlnx_pcie_xvc_config",
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.handler = xlnx_pcie_xvc_handle_config_command,
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.mode = COMMAND_CONFIG,
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.help = "Configure XVC/PCIe JTAG adapter",
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.usage = "device",
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},
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COMMAND_REGISTRATION_DONE
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};
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static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
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.execute_queue = &xlnx_pcie_xvc_execute_queue,
|
|
};
|
|
|
|
static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
|
|
{
|
|
size_t left, write;
|
|
uint32_t send;
|
|
int err;
|
|
|
|
left = length;
|
|
while (left) {
|
|
write = MIN(XLNX_XVC_MAX_BITS, left);
|
|
send = buf_get_u32(seq, 0, write);
|
|
err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
|
|
if (err != ERROR_OK)
|
|
return err;
|
|
left -= write;
|
|
seq += sizeof(uint32_t);
|
|
};
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
|
|
{
|
|
switch (seq) {
|
|
case LINE_RESET:
|
|
LOG_DEBUG("SWD line reset");
|
|
return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
|
|
swd_seq_line_reset_len);
|
|
case JTAG_TO_SWD:
|
|
LOG_DEBUG("JTAG-to-SWD");
|
|
return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
|
|
swd_seq_jtag_to_swd_len);
|
|
case SWD_TO_JTAG:
|
|
LOG_DEBUG("SWD-to-JTAG");
|
|
return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
|
|
swd_seq_swd_to_jtag_len);
|
|
default:
|
|
LOG_ERROR("Sequence %d not supported", seq);
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int queued_retval;
|
|
|
|
static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
|
|
uint32_t ap_delay_clk);
|
|
|
|
static void swd_clear_sticky_errors(void)
|
|
{
|
|
xlnx_pcie_xvc_swd_write_reg(swd_cmd(false, false, DP_ABORT),
|
|
STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
|
|
}
|
|
|
|
static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
|
|
uint32_t ap_delay_clk)
|
|
{
|
|
uint32_t res, ack, rpar;
|
|
int err;
|
|
|
|
assert(cmd & SWD_CMD_RnW);
|
|
|
|
cmd |= SWD_CMD_START | SWD_CMD_PARK;
|
|
/* cmd + ack */
|
|
err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
ack = MASK_ACK(res);
|
|
|
|
/* read data */
|
|
err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
/* parity + trn */
|
|
err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
|
|
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
|
|
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
|
|
cmd & SWD_CMD_APnDP ? "AP" : "DP",
|
|
cmd & SWD_CMD_RnW ? "read" : "write",
|
|
(cmd & SWD_CMD_A32) >> 1,
|
|
res);
|
|
switch (ack) {
|
|
case SWD_ACK_OK:
|
|
if (MASK_PAR(rpar) != parity_u32(res)) {
|
|
LOG_DEBUG_IO("Wrong parity detected");
|
|
queued_retval = ERROR_FAIL;
|
|
return;
|
|
}
|
|
if (value)
|
|
*value = res;
|
|
if (cmd & SWD_CMD_APnDP)
|
|
err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
|
|
queued_retval = err;
|
|
return;
|
|
case SWD_ACK_WAIT:
|
|
LOG_DEBUG_IO("SWD_ACK_WAIT");
|
|
swd_clear_sticky_errors();
|
|
return;
|
|
case SWD_ACK_FAULT:
|
|
LOG_DEBUG_IO("SWD_ACK_FAULT");
|
|
queued_retval = ack;
|
|
return;
|
|
default:
|
|
LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
|
|
queued_retval = ack;
|
|
return;
|
|
}
|
|
err_out:
|
|
queued_retval = err;
|
|
}
|
|
|
|
static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
|
|
uint32_t ap_delay_clk)
|
|
{
|
|
uint32_t res, ack;
|
|
int err;
|
|
|
|
assert(!(cmd & SWD_CMD_RnW));
|
|
|
|
cmd |= SWD_CMD_START | SWD_CMD_PARK;
|
|
/* cmd + trn + ack */
|
|
err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
ack = MASK_ACK(res);
|
|
|
|
/* write data */
|
|
err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
/* parity + trn */
|
|
err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
|
|
if (err != ERROR_OK)
|
|
goto err_out;
|
|
|
|
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
|
|
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
|
|
"WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
|
|
cmd & SWD_CMD_APnDP ? "AP" : "DP",
|
|
cmd & SWD_CMD_RnW ? "read" : "write",
|
|
(cmd & SWD_CMD_A32) >> 1,
|
|
value);
|
|
|
|
switch (ack) {
|
|
case SWD_ACK_OK:
|
|
if (cmd & SWD_CMD_APnDP)
|
|
err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
|
|
queued_retval = err;
|
|
return;
|
|
case SWD_ACK_WAIT:
|
|
LOG_DEBUG_IO("SWD_ACK_WAIT");
|
|
swd_clear_sticky_errors();
|
|
return;
|
|
case SWD_ACK_FAULT:
|
|
LOG_DEBUG_IO("SWD_ACK_FAULT");
|
|
queued_retval = ack;
|
|
return;
|
|
default:
|
|
LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
|
|
queued_retval = ack;
|
|
return;
|
|
}
|
|
|
|
err_out:
|
|
queued_retval = err;
|
|
}
|
|
|
|
static int xlnx_pcie_xvc_swd_run_queue(void)
|
|
{
|
|
int err;
|
|
|
|
/* we want at least 8 idle cycles between each transaction */
|
|
err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
|
|
if (err != ERROR_OK)
|
|
return err;
|
|
|
|
err = queued_retval;
|
|
queued_retval = ERROR_OK;
|
|
LOG_DEBUG("SWD queue return value: %02x", err);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int xlnx_pcie_xvc_swd_init(void)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
|
|
.init = xlnx_pcie_xvc_swd_init,
|
|
.switch_seq = xlnx_pcie_xvc_swd_switch_seq,
|
|
.read_reg = xlnx_pcie_xvc_swd_read_reg,
|
|
.write_reg = xlnx_pcie_xvc_swd_write_reg,
|
|
.run = xlnx_pcie_xvc_swd_run_queue,
|
|
};
|
|
|
|
static const char * const xlnx_pcie_xvc_transports[] = { "jtag", "swd", NULL };
|
|
|
|
struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
|
|
.name = "xlnx_pcie_xvc",
|
|
.transports = xlnx_pcie_xvc_transports,
|
|
.commands = xlnx_pcie_xvc_command_handlers,
|
|
|
|
.init = &xlnx_pcie_xvc_init,
|
|
.quit = &xlnx_pcie_xvc_quit,
|
|
|
|
.jtag_ops = &xlnx_pcie_xvc_jtag_ops,
|
|
.swd_ops = &xlnx_pcie_xvc_swd_ops,
|
|
};
|