openocd/src/target/riscv
Marc Schink fb43f1ff4e target: Rework 'set' variable of break-/watchpoints
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.

This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.

In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.

In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.

While at it, fix a few coding style issues.

Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19 09:14:39 +00:00
..
asm.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
batch.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
batch.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
debug_defines.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
encoding.h riscv: Regenerated debug_defines.h and encoding.h 2021-11-20 14:39:13 +00:00
gdb_regs.h Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
Makefile.am Add RISC-V support. 2018-07-24 13:07:26 +01:00
opcodes.h Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
program.c Upstream tons of RISC-V changes. 2020-10-14 05:43:05 +01:00
program.h Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
riscv_semihosting.c semihosting: User defined operation, Tcl command exec on host 2022-02-05 21:40:17 +00:00
riscv-011.c Upstream a whole host of RISC-V changes. 2021-10-25 16:12:05 +00:00
riscv-013.c Fix small memory leak. 2022-02-14 15:13:11 +00:00
riscv.c target: Rework 'set' variable of break-/watchpoints 2022-03-19 09:14:39 +00:00
riscv.h target/riscv: calloc() memory per register. 2021-12-24 15:10:20 +00:00