1457a1ab42
A JTAG TAP for boundary scan should be added in the scan chain through the command "jtag newtap". In some TCL target script the boundary scan TAP is added through the command "swj_newdap", command that is inappropriate in this context because specific for arm adi-v5 SWJ-DP. This situation was probably created to bypass the error with HLA framework, caused by missing command "jtag newtap". Add the command "jtag newtap" in HLA, by reusing the existing code for command "hla newtap". Fix the TCL target scripts to use the command "jtag newtap" for the boundary scan TAPs. The TCL script target/psoc6.cfg has no evident reference to HLA, so the reason for using "swj_newdap" is less clear. Nevertheless it uses the wrong command and, once HLA is fixed, there is no reason to avoid fixing it too. Change-Id: Ia92f8221430cf6f3d2c34294e22e5e18963bb88c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4873 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
151 lines
4.0 KiB
INI
151 lines
4.0 KiB
INI
#
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# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
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# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
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# the same Flash/RAM/MMIO address space.
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#
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source [find target/swj-dp.tcl]
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adapter speed 1000
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global _CHIPNAME
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME psoc6
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}
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global TARGET
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set TARGET $_CHIPNAME.cpu
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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# Is CM0 Debugging enabled ?
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global _ENABLE_CM0
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if { [info exists ENABLE_CM0] } {
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set _ENABLE_CM0 $ENABLE_CM0
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} else {
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set _ENABLE_CM0 1
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}
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# Is CM4 Debugging enabled ?
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global _ENABLE_CM4
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if { [info exists ENABLE_CM4] } {
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set _ENABLE_CM4 $ENABLE_CM4
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} else {
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set _ENABLE_CM4 1
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}
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global _WORKAREASIZE_CM0
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if { [info exists WORKAREASIZE_CM0] } {
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set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
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} else {
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set _WORKAREASIZE_CM0 0x4000
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}
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global _WORKAREASIZE_CM4
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if { [info exists WORKAREASIZE_CM4] } {
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set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
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} else {
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set _WORKAREASIZE_CM4 0x4000
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}
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global _WORKAREAADDR_CM0
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if { [info exists WORKAREAADDR_CM0] } {
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set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
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} else {
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set _WORKAREAADDR_CM0 0x08000000
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}
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global _WORKAREAADDR_CM4
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if { [info exists WORKAREAADDR_CM4] } {
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set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
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} else {
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set _WORKAREAADDR_CM4 0x08000000
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}
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proc init_reset { mode } {
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global RESET_MODE
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set RESET_MODE $mode
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if {[using_jtag]} {
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jtag arp_init-reset
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}
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}
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# Utility to make 'reset halt' work as reset;halt on a target
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# It does not prevent running code after reset
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proc psoc6_deassert_post { target } {
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# PSoC6 cleared AP registers including TAR during reset
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# Force examine to synchronize OpenOCD target status
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$target arp_examine
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global RESET_MODE
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global TARGET
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if { $RESET_MODE ne "run" } {
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$target arp_poll
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$target arp_poll
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set st [$target curstate]
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if { $st eq "reset" } {
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# we assume running state follows
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# if reset accidentally halts, waiting is useless
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catch { $target arp_waitstate running 100 }
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set st [$target curstate]
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}
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if { $st eq "running" } {
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echo "$target: Ran after reset and before halt..."
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if { $target eq "${TARGET}.cm0" } {
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# Try to cleanly reset whole system
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# and halt the CM0 at entry point
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psoc6 reset_halt
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$target arp_waitstate halted 100
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} else {
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$target arp_halt
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}
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}
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}
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}
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if { $_ENABLE_CM0 } {
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target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
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${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
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flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
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flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0
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flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
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flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
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flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
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flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
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${TARGET}.cm0 cortex_m reset_config sysresetreq
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${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
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}
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if { $_ENABLE_CM4 } {
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target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
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${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
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flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
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flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4
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flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
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flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
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flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
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flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
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${TARGET}.cm4 cortex_m reset_config vectreset
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${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
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}
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if { $_ENABLE_CM0 } {
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# Use CM0+ by default on dual-core devices
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targets ${TARGET}.cm0
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}
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
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}
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