f5657aa76e
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.
Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
#!/usr/bin/perl -Wpi
my $re_sym = qr{[a-z_][a-z0-9_]*}i;
my $re_var = qr{(?:\$|\$::)$re_sym};
my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
my $re_op = qr{<<|>>|[+\-*/&|]};
my $re_expr = qr{(
(?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
\s*$re_op\s*
(?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
)}x;
# [expr [dict get $regsC100 SYM] + HEXNUM]
s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;
# [ expr (EXPR) ]
# [ expr EXPR ]
# note: $re_expr captures '$3'
s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
87 lines
2.5 KiB
INI
87 lines
2.5 KiB
INI
# Copyright (C) 2019,2020 Synopsys, Inc.
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# Anton Kolesov <anton.kolesov@synopsys.com>
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# Didin Evgeniy <didin@synopsys.com>
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#
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr {$_coreid << 13}]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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# ARC HS38 core 4
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set _TARGETNAME $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {$_coreid << 13}]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 3
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set _TARGETNAME $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {$_coreid << 13}]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 2
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set _TARGETNAME $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {$_coreid << 13}]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME arc cache l2 auto 1
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# ARC HS38 core 1
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set _TARGETNAME $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
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$_TARGETNAME configure -coreid $_coreid
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$_TARGETNAME configure -dbgbase $_dbgbase
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$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME arc cache l2 auto 1
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