b8fd9aecb1
this is a rework of #5320 started by Andreas then abandoned. same syntax as in stm32f2x driver: enable OTP for writing > stm32l4x otp 1 enable write to OTP > flash write_bank 1 foo.bin 0 > flash filld 0x1FFF7000 0xDeadBeafBaadF00d 1 read OTP > mdw 0x1FFF7000 4 disable OTP > stm32l4x otp 1 disable Change-Id: Id7d7c163b35d7a3f406dc200d7e2fc293b0675c2 Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: http://openocd.zylin.com/5537 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
104 lines
2.6 KiB
INI
104 lines
2.6 KiB
INI
# script for stm32g4x family
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#
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# stm32g4 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32g4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0440
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# Section 46.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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# reasonable default
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event reset-init {
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# CPU comes out of reset with HSION | HSIRDY.
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# Use HSI 16 MHz clock, compliant even with VOS == 2.
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# 1 WS compliant with VOS == 2 and 16 MHz.
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mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
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mmw 0x40021000 0x00000100 0x00000000 ;# RCC_CR |= HSION
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mmw 0x40021008 0x00000001 0x00000002 ;# RCC_CFGR: SW=HSI16
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is HSI (16 MHz)
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adapter speed 2000
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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