c5eb990825
This patch adds support for instruction tracing to eSi-RISC targets. The command interface is borrowed heavily from ETM; eSi-Trace uses a less sophisticated model for tracing, however the setup and usage is similar. This patch also cleans up the command interfaces of the other esirisc command groups and adds additional debugging information to log messages when dealing with CSRs. This patch "finalizes" support for 32-bit eSi-RISC targets. Change-Id: Ia2a9de79a3c7c066240b5212721fb1b7584a9a45 Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4780 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
237 lines
4.1 KiB
Makefile
237 lines
4.1 KiB
Makefile
if OOCD_TRACE
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OOCD_TRACE_FILES = %D%/oocd_trace.c
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else
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OOCD_TRACE_FILES =
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endif
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%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
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%D%/riscv/libriscv.la
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STARTUP_TCL_SRCS += %D%/startup.tcl
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noinst_LTLIBRARIES += %D%/libtarget.la
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%C%_libtarget_la_SOURCES = \
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$(TARGET_CORE_SRC) \
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$(ARM_DEBUG_SRC) \
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$(ARMV4_5_SRC) \
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$(ARMV6_SRC) \
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$(ARMV7_SRC) \
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$(ARM_MISC_SRC) \
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$(AVR32_SRC) \
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$(MIPS32_SRC) \
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$(NDS32_SRC) \
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$(STM8_SRC) \
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$(INTEL_IA32_SRC) \
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$(ESIRISC_SRC) \
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%D%/avrt.c \
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%D%/dsp563xx.c \
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%D%/dsp563xx_once.c \
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%D%/dsp5680xx.c \
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%D%/hla_target.c
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if TARGET64
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%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
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endif
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TARGET_CORE_SRC = \
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%D%/algorithm.c \
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%D%/register.c \
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%D%/image.c \
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%D%/breakpoints.c \
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%D%/target.c \
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%D%/target_request.c \
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%D%/testee.c \
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%D%/semihosting_common.c \
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%D%/smp.c
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ARMV4_5_SRC = \
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%D%/armv4_5.c \
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%D%/armv4_5_mmu.c \
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%D%/armv4_5_cache.c \
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$(ARM7_9_SRC)
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ARM7_9_SRC = \
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%D%/arm7_9_common.c \
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%D%/arm7tdmi.c \
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%D%/arm720t.c \
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%D%/arm9tdmi.c \
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%D%/arm920t.c \
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%D%/arm966e.c \
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%D%/arm946e.c \
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%D%/arm926ejs.c \
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%D%/feroceon.c
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ARM_MISC_SRC = \
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%D%/fa526.c \
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%D%/xscale.c
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ARMV6_SRC = \
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%D%/arm11.c \
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%D%/arm11_dbgtap.c
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ARMV7_SRC = \
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%D%/armv7m.c \
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%D%/armv7m_trace.c \
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%D%/cortex_m.c \
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%D%/armv7a.c \
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%D%/armv7a_mmu.c \
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%D%/cortex_a.c \
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%D%/ls1_sap.c \
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%D%/mem_ap.c
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ARMV8_SRC = \
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%D%/armv8_dpm.c \
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%D%/armv8_opcodes.c \
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%D%/aarch64.c \
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%D%/armv8.c \
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%D%/armv8_cache.c
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ARM_DEBUG_SRC = \
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%D%/arm_dpm.c \
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%D%/arm_jtag.c \
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%D%/arm_disassembler.c \
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%D%/arm_simulator.c \
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%D%/arm_semihosting.c \
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%D%/arm_adi_v5.c \
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%D%/arm_dap.c \
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%D%/armv7a_cache.c \
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%D%/armv7a_cache_l2x.c \
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%D%/adi_v5_jtag.c \
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%D%/adi_v5_swd.c \
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%D%/embeddedice.c \
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%D%/trace.c \
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%D%/etb.c \
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%D%/etm.c \
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$(OOCD_TRACE_FILES) \
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%D%/etm_dummy.c \
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%D%/arm_cti.c
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AVR32_SRC = \
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%D%/avr32_ap7k.c \
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%D%/avr32_jtag.c \
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%D%/avr32_mem.c \
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%D%/avr32_regs.c
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MIPS32_SRC = \
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%D%/mips32.c \
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%D%/mips_m4k.c \
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%D%/mips32_pracc.c \
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%D%/mips32_dmaacc.c \
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%D%/mips_ejtag.c
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NDS32_SRC = \
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%D%/nds32.c \
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%D%/nds32_reg.c \
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%D%/nds32_cmd.c \
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%D%/nds32_disassembler.c \
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%D%/nds32_tlb.c \
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%D%/nds32_v2.c \
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%D%/nds32_v3_common.c \
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%D%/nds32_v3.c \
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%D%/nds32_v3m.c \
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%D%/nds32_aice.c
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STM8_SRC = \
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%D%/stm8.c
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INTEL_IA32_SRC = \
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%D%/quark_x10xx.c \
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%D%/quark_d20xx.c \
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%D%/lakemont.c \
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%D%/x86_32_common.c
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ESIRISC_SRC = \
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%D%/esirisc.c \
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%D%/esirisc_jtag.c \
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%D%/esirisc_trace.c
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%C%_libtarget_la_SOURCES += \
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%D%/algorithm.h \
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%D%/arm.h \
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%D%/arm_dpm.h \
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%D%/arm_jtag.h \
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%D%/arm_adi_v5.h \
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%D%/armv7a_cache.h \
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%D%/armv7a_cache_l2x.h \
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%D%/armv7a_mmu.h \
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%D%/arm_disassembler.h \
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%D%/arm_opcodes.h \
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%D%/arm_simulator.h \
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%D%/arm_semihosting.h \
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%D%/arm7_9_common.h \
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%D%/arm7tdmi.h \
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%D%/arm720t.h \
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%D%/arm9tdmi.h \
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%D%/arm920t.h \
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%D%/arm926ejs.h \
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%D%/arm966e.h \
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%D%/arm946e.h \
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%D%/arm11.h \
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%D%/arm11_dbgtap.h \
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%D%/armv4_5.h \
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%D%/armv4_5_mmu.h \
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%D%/armv4_5_cache.h \
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%D%/armv7a.h \
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%D%/armv7m.h \
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%D%/armv7m_trace.h \
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%D%/armv8.h \
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%D%/armv8_dpm.h \
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%D%/armv8_opcodes.h \
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%D%/armv8_cache.h \
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%D%/avrt.h \
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%D%/dsp563xx.h \
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%D%/dsp563xx_once.h \
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%D%/dsp5680xx.h \
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%D%/breakpoints.h \
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%D%/cortex_m.h \
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%D%/cortex_a.h \
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%D%/aarch64.h \
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%D%/embeddedice.h \
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%D%/etb.h \
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%D%/etm.h \
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%D%/etm_dummy.h \
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%D%/image.h \
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%D%/mips32.h \
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%D%/mips_m4k.h \
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%D%/mips_ejtag.h \
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%D%/mips32_pracc.h \
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%D%/mips32_dmaacc.h \
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%D%/oocd_trace.h \
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%D%/register.h \
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%D%/target.h \
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%D%/target_type.h \
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%D%/trace.h \
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%D%/target_request.h \
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%D%/trace.h \
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%D%/xscale.h \
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%D%/smp.h \
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%D%/avr32_ap7k.h \
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%D%/avr32_jtag.h \
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%D%/avr32_mem.h \
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%D%/avr32_regs.h \
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%D%/nds32.h \
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%D%/nds32_cmd.h \
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%D%/nds32_disassembler.h \
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%D%/nds32_edm.h \
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%D%/nds32_insn.h \
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%D%/nds32_reg.h \
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%D%/nds32_tlb.h \
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%D%/nds32_v2.h \
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%D%/nds32_v3_common.h \
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%D%/nds32_v3.h \
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%D%/nds32_v3m.h \
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%D%/nds32_aice.h \
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%D%/semihosting_common.h \
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%D%/stm8.h \
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%D%/lakemont.h \
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%D%/x86_32_common.h \
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%D%/arm_cti.h \
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%D%/esirisc.h \
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%D%/esirisc_jtag.h \
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%D%/esirisc_regs.h \
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%D%/esirisc_trace.h
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include %D%/openrisc/Makefile.am
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include %D%/riscv/Makefile.am
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