55eeea7fce
Save and display the address of the instruction which triggered the watchpoint. Because of pipelining, that's well behind the PC value when debug entry completes. (Example in a subroutine that had been returned from...) Remove unused A8 stuff, mostly watchpoint hooks from the header. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/***************************************************************************
|
|
* Copyright (C) 2005 by Dominic Rath *
|
|
* Dominic.Rath@gmx.de *
|
|
* *
|
|
* Copyright (C) 2006 by Magnus Lundin *
|
|
* lundin@mlu.mine.nu *
|
|
* *
|
|
* Copyright (C) 2008 by Spencer Oliver *
|
|
* spen@spen-soft.co.uk *
|
|
* *
|
|
* Copyright (C) 2009 by Dirk Behme *
|
|
* dirk.behme@gmail.com - copy from cortex_m3 *
|
|
* *
|
|
* This program is free software; you can redistribute it and/or modify *
|
|
* it under the terms of the GNU General Public License as published by *
|
|
* the Free Software Foundation; either version 2 of the License, or *
|
|
* (at your option) any later version. *
|
|
* *
|
|
* This program is distributed in the hope that it will be useful, *
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
|
* GNU General Public License for more details. *
|
|
* *
|
|
* You should have received a copy of the GNU General Public License *
|
|
* along with this program; if not, write to the *
|
|
* Free Software Foundation, Inc., *
|
|
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
|
***************************************************************************/
|
|
#ifndef CORTEX_A8_H
|
|
#define CORTEX_A8_H
|
|
|
|
#include "armv7a.h"
|
|
|
|
extern char* cortex_a8_state_strings[];
|
|
|
|
#define CORTEX_A8_COMMON_MAGIC 0x411fc082
|
|
|
|
/* See Cortex-A8 TRM section 12.5 */
|
|
#define CPUDBG_CPUID 0xD00
|
|
#define CPUDBG_CTYPR 0xD04
|
|
#define CPUDBG_TTYPR 0xD0C
|
|
#define CPUDBG_LOCKACCESS 0xFB0
|
|
#define CPUDBG_LOCKSTATUS 0xFB4
|
|
|
|
#define BRP_NORMAL 0
|
|
#define BRP_CONTEXT 1
|
|
|
|
struct cortex_a8_brp
|
|
{
|
|
int used;
|
|
int type;
|
|
uint32_t value;
|
|
uint32_t control;
|
|
uint8_t BRPn;
|
|
};
|
|
|
|
struct cortex_a8_common
|
|
{
|
|
int common_magic;
|
|
struct arm_jtag jtag_info;
|
|
|
|
/* Context information */
|
|
uint32_t cpudbg_dscr;
|
|
|
|
/* Saved cp15 registers */
|
|
uint32_t cp15_control_reg;
|
|
|
|
/* Breakpoint register pairs */
|
|
int brp_num_context;
|
|
int brp_num;
|
|
int brp_num_available;
|
|
struct cortex_a8_brp *brp_list;
|
|
|
|
/* Use cortex_a8_read_regs_through_mem for fast register reads */
|
|
int fast_reg_read;
|
|
|
|
struct armv7a_common armv7a_common;
|
|
};
|
|
|
|
static inline struct cortex_a8_common *
|
|
target_to_cortex_a8(struct target *target)
|
|
{
|
|
return container_of(target->arch_info, struct cortex_a8_common,
|
|
armv7a_common.armv4_5_common);
|
|
}
|
|
|
|
#endif /* CORTEX_A8_H */
|