04b514707f
We have too many different registers, and too many version and context dependent interpretations, for this type of bitfield management to be scalable. (Anyone who really wants bitfield interpretation *can* do that in Tcl code...) There are ... quite a few copies of the same ARM dummy registers. There should eventually be one copy; this many is craziness. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
465 lines
12 KiB
C
465 lines
12 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "mips32.h"
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char* mips32_core_reg_list[] =
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{
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"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
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"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
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"status", "lo", "hi", "badvaddr", "cause", "pc"
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};
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struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
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{
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{0, NULL, NULL},
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{1, NULL, NULL},
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{2, NULL, NULL},
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{3, NULL, NULL},
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{4, NULL, NULL},
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{5, NULL, NULL},
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{6, NULL, NULL},
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{7, NULL, NULL},
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{8, NULL, NULL},
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{9, NULL, NULL},
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{10, NULL, NULL},
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{11, NULL, NULL},
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{12, NULL, NULL},
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{13, NULL, NULL},
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{14, NULL, NULL},
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{15, NULL, NULL},
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{16, NULL, NULL},
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{17, NULL, NULL},
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{18, NULL, NULL},
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{19, NULL, NULL},
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{20, NULL, NULL},
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{21, NULL, NULL},
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{22, NULL, NULL},
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{23, NULL, NULL},
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{24, NULL, NULL},
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{25, NULL, NULL},
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{26, NULL, NULL},
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{27, NULL, NULL},
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{28, NULL, NULL},
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{29, NULL, NULL},
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{30, NULL, NULL},
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{31, NULL, NULL},
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{32, NULL, NULL},
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{33, NULL, NULL},
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{34, NULL, NULL},
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{35, NULL, NULL},
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{36, NULL, NULL},
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{37, NULL, NULL},
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};
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/* number of mips dummy fp regs fp0 - fp31 + fsr and fir
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* we also add 18 unknown registers to handle gdb requests */
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#define MIPS32NUMFPREGS 34 + 18
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uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
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struct reg mips32_gdb_dummy_fp_reg =
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{
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.name = "GDB dummy floating-point register",
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.value = mips32_gdb_dummy_fp_value,
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.dirty = 0,
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.valid = 1,
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.size = 32,
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.arch_info = NULL,
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.arch_type = 0,
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};
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int mips32_core_reg_arch_type = -1;
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int mips32_get_core_reg(struct reg *reg)
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{
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int retval;
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struct mips32_core_reg *mips32_reg = reg->arch_info;
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struct target *target = mips32_reg->target;
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struct mips32_common *mips32_target = target->arch_info;
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if (target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = mips32_target->read_core_reg(target, mips32_reg->num);
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return retval;
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}
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int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
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{
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struct mips32_core_reg *mips32_reg = reg->arch_info;
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struct target *target = mips32_reg->target;
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uint32_t value = buf_get_u32(buf, 0, 32);
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if (target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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buf_set_u32(reg->value, 0, 32, value);
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reg->dirty = 1;
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reg->valid = 1;
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return ERROR_OK;
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}
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int mips32_read_core_reg(struct target *target, int num)
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{
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uint32_t reg_value;
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struct mips32_core_reg *mips_core_reg;
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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if ((num < 0) || (num >= MIPS32NUMCOREREGS))
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return ERROR_INVALID_ARGUMENTS;
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mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
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reg_value = mips32->core_regs[num];
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buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
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mips32->core_cache->reg_list[num].valid = 1;
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mips32->core_cache->reg_list[num].dirty = 0;
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return ERROR_OK;
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}
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int mips32_write_core_reg(struct target *target, int num)
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{
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uint32_t reg_value;
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struct mips32_core_reg *mips_core_reg;
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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if ((num < 0) || (num >= MIPS32NUMCOREREGS))
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return ERROR_INVALID_ARGUMENTS;
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reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
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mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
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mips32->core_regs[num] = reg_value;
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LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
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mips32->core_cache->reg_list[num].valid = 1;
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mips32->core_cache->reg_list[num].dirty = 0;
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return ERROR_OK;
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}
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int mips32_invalidate_core_regs(struct target *target)
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{
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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int i;
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for (i = 0; i < mips32->core_cache->num_regs; i++)
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{
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mips32->core_cache->reg_list[i].valid = 0;
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mips32->core_cache->reg_list[i].dirty = 0;
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}
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return ERROR_OK;
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}
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int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
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{
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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int i;
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/* include floating point registers */
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*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
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*reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
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for (i = 0; i < MIPS32NUMCOREREGS; i++)
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{
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(*reg_list)[i] = &mips32->core_cache->reg_list[i];
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}
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/* add dummy floating points regs */
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for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
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{
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(*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
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}
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return ERROR_OK;
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}
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int mips32_save_context(struct target *target)
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{
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int i;
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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/* read core registers */
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mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
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for (i = 0; i < MIPS32NUMCOREREGS; i++)
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{
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if (!mips32->core_cache->reg_list[i].valid)
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{
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mips32->read_core_reg(target, i);
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}
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}
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return ERROR_OK;
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}
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int mips32_restore_context(struct target *target)
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{
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int i;
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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for (i = 0; i < MIPS32NUMCOREREGS; i++)
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{
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if (mips32->core_cache->reg_list[i].dirty)
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{
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mips32->write_core_reg(target, i);
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}
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}
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/* write core regs */
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mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
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return ERROR_OK;
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}
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int mips32_arch_state(struct target *target)
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{
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struct mips32_common *mips32 = target->arch_info;
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if (mips32->common_magic != MIPS32_COMMON_MAGIC)
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{
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LOG_ERROR("BUG: called for a non-MIPS32 target");
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exit(-1);
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}
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LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
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Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
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buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
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return ERROR_OK;
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}
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struct reg_cache *mips32_build_reg_cache(struct target *target)
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{
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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int num_regs = MIPS32NUMCOREREGS;
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
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struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
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int i;
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if (mips32_core_reg_arch_type == -1)
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mips32_core_reg_arch_type = register_reg_arch_type(mips32_get_core_reg, mips32_set_core_reg);
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register_init_dummy(&mips32_gdb_dummy_fp_reg);
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/* Build the process context cache */
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cache->name = "mips32 registers";
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cache->next = NULL;
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cache->reg_list = reg_list;
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cache->num_regs = num_regs;
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(*cache_p) = cache;
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mips32->core_cache = cache;
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for (i = 0; i < num_regs; i++)
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{
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arch_info[i] = mips32_core_reg_list_arch_info[i];
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arch_info[i].target = target;
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arch_info[i].mips32_common = mips32;
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reg_list[i].name = mips32_core_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].arch_type = mips32_core_reg_arch_type;
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reg_list[i].arch_info = &arch_info[i];
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}
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return cache;
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}
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int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, struct jtag_tap *tap)
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{
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target->arch_info = mips32;
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mips32->common_magic = MIPS32_COMMON_MAGIC;
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/* has breakpoint/watchpint unit been scanned */
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mips32->bp_scanned = 0;
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mips32->data_break_list = NULL;
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mips32->ejtag_info.tap = tap;
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mips32->read_core_reg = mips32_read_core_reg;
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mips32->write_core_reg = mips32_write_core_reg;
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return ERROR_OK;
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}
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int mips32_register_commands(struct command_context *cmd_ctx)
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{
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return ERROR_OK;
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}
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int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
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{
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/*TODO*/
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return ERROR_OK;
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}
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int mips32_examine(struct target *target)
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{
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struct mips32_common *mips32 = target->arch_info;
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if (!target_was_examined(target))
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{
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target_set_examined(target);
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/* we will configure later */
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mips32->bp_scanned = 0;
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mips32->num_inst_bpoints = 0;
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mips32->num_data_bpoints = 0;
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mips32->num_inst_bpoints_avail = 0;
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mips32->num_data_bpoints_avail = 0;
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}
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return ERROR_OK;
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}
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int mips32_configure_break_unit(struct target *target)
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{
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target->arch_info;
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int retval;
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uint32_t dcr, bpinfo;
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int i;
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if (mips32->bp_scanned)
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return ERROR_OK;
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/* get info about breakpoint support */
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if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
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return retval;
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if (dcr & (1 << 16))
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{
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/* get number of inst breakpoints */
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if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
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return retval;
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mips32->num_inst_bpoints = (bpinfo >> 24) & 0x0F;
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mips32->num_inst_bpoints_avail = mips32->num_inst_bpoints;
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mips32->inst_break_list = calloc(mips32->num_inst_bpoints, sizeof(struct mips32_comparator));
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for (i = 0; i < mips32->num_inst_bpoints; i++)
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{
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mips32->inst_break_list[i].reg_address = EJTAG_IBA1 + (0x100 * i);
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}
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/* clear IBIS reg */
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if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
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return retval;
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}
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if (dcr & (1 << 17))
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{
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/* get number of data breakpoints */
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if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
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return retval;
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mips32->num_data_bpoints = (bpinfo >> 24) & 0x0F;
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mips32->num_data_bpoints_avail = mips32->num_data_bpoints;
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mips32->data_break_list = calloc(mips32->num_data_bpoints, sizeof(struct mips32_comparator));
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for (i = 0; i < mips32->num_data_bpoints; i++)
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{
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mips32->data_break_list[i].reg_address = EJTAG_DBA1 + (0x100 * i);
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}
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/* clear DBIS reg */
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if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
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return retval;
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}
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LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
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mips32->bp_scanned = 1;
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return ERROR_OK;
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}
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int mips32_enable_interrupts(struct target *target, int enable)
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{
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int retval;
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int update = 0;
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uint32_t dcr;
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/* read debug control register */
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if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
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return retval;
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if (enable)
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{
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if (!(dcr & (1 << 4)))
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{
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/* enable interrupts */
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dcr |= (1 << 4);
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update = 1;
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}
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}
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else
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{
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if (dcr & (1 << 4))
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{
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/* disable interrupts */
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dcr &= ~(1 << 4);
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update = 1;
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}
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}
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if (update)
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{
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if ((retval = target_write_u32(target, EJTAG_DCR, dcr)) != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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