5ed126c4f9
- fixed compiler warnings throughout the code (thanks to Vincent Palatin for this patch) - added support for accessing ETB (embedded trace buffer) registers git-svn-id: svn://svn.berlios.de/openocd/trunk@134 b42882b7-edfa-0310-969c-e2dbd0fdcd60
320 lines
8.3 KiB
C
320 lines
8.3 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "etb.h"
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#include "log.h"
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#include "types.h"
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#include "binarybuffer.h"
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#include "target.h"
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#include "register.h"
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#include "jtag.h"
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#include <stdlib.h>
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char* etb_reg_list[] =
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{
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"ETB_identification",
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"ETB_ram_depth",
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"ETB_ram_width",
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"ETB_status",
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"ETB_ram_data",
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"ETB_ram_read_pointer",
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"ETB_ram_write_pointer",
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"ETB_trigger_counter",
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"ETB_control",
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};
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int etb_reg_arch_type = -1;
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int etb_get_reg(reg_t *reg);
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int etb_set_reg(reg_t *reg, u32 value);
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int etb_set_reg_w_exec(reg_t *reg, u8 *buf);
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int etb_write_reg(reg_t *reg, u32 value);
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int etb_read_reg(reg_t *reg);
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int etb_set_instr(etb_t *etb, u32 new_instr)
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{
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jtag_device_t *device = jtag_get_device(etb->chain_pos);
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if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
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{
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scan_field_t field;
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field.device = etb->chain_pos;
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field.num_bits = device->ir_length;
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field.out_value = calloc(CEIL(field.num_bits, 8), 1);
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buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
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field.out_mask = NULL;
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field.in_value = NULL;
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field.in_check_value = NULL;
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field.in_check_mask = NULL;
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field.in_handler = NULL;
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field.in_handler_priv = NULL;
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jtag_add_ir_scan(1, &field, -1);
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free(field.out_value);
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}
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return ERROR_OK;
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}
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int etb_scann(etb_t *etb, u32 new_scan_chain)
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{
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if(etb->cur_scan_chain != new_scan_chain)
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{
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scan_field_t field;
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field.device = etb->chain_pos;
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field.num_bits = 5;
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field.out_value = calloc(CEIL(field.num_bits, 8), 1);
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buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
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field.out_mask = NULL;
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field.in_value = NULL;
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field.in_check_value = NULL;
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field.in_check_mask = NULL;
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field.in_handler = NULL;
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field.in_handler_priv = NULL;
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/* select INTEST instruction */
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etb_set_instr(etb, 0x2);
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jtag_add_dr_scan(1, &field, -1);
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etb->cur_scan_chain = new_scan_chain;
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free(field.out_value);
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}
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return ERROR_OK;
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}
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reg_cache_t* etb_build_reg_cache(etb_t *etb)
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{
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reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = NULL;
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etb_reg_t *arch_info = NULL;
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int num_regs = 9;
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int i;
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/* register a register arch-type for etm registers only once */
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if (etb_reg_arch_type == -1)
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etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
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/* the actual registers are kept in two arrays */
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reg_list = calloc(num_regs, sizeof(reg_t));
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arch_info = calloc(num_regs, sizeof(etb_reg_t));
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/* fill in values for the reg cache */
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reg_cache->name = "etb registers";
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reg_cache->next = NULL;
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reg_cache->reg_list = reg_list;
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reg_cache->num_regs = num_regs;
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/* set up registers */
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for (i = 0; i < num_regs; i++)
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{
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reg_list[i].name = etb_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].bitfield_desc = NULL;
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reg_list[i].num_bitfields = 0;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].arch_type = etb_reg_arch_type;
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reg_list[i].size = 32;
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arch_info[i].addr = i;
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arch_info[i].etb = etb;
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}
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return reg_cache;
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}
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int etb_get_reg(reg_t *reg)
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{
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if (etb_read_reg(reg) != ERROR_OK)
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{
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ERROR("BUG: error scheduling etm register read");
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exit(-1);
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}
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if (jtag_execute_queue() != ERROR_OK)
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{
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ERROR("register read failed");
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}
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return ERROR_OK;
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}
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int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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{
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etb_reg_t *etb_reg = reg->arch_info;
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u8 reg_addr = etb_reg->addr & 0x7f;
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scan_field_t fields[3];
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DEBUG("%i", etb_reg->addr);
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jtag_add_end_state(TAP_RTI);
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etb_scann(etb_reg->etb, 0x0);
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etb_set_instr(etb_reg->etb, 0xc);
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fields[0].device = etb_reg->etb->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = reg->value;
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fields[0].out_mask = NULL;
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fields[0].in_value = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = etb_reg->etb->chain_pos;
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fields[1].num_bits = 7;
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fields[1].out_value = malloc(1);
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = etb_reg->etb->chain_pos;
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fields[2].num_bits = 1;
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fields[2].out_value = malloc(1);
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buf_set_u32(fields[2].out_value, 0, 1, 0);
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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fields[0].in_value = reg->value;
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fields[0].in_check_value = check_value;
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fields[0].in_check_mask = check_mask;
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jtag_add_dr_scan(3, fields, -1);
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free(fields[1].out_value);
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free(fields[2].out_value);
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return ERROR_OK;
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}
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int etb_read_reg(reg_t *reg)
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{
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return etb_read_reg_w_check(reg, NULL, NULL);
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}
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int etb_set_reg(reg_t *reg, u32 value)
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{
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if (etb_write_reg(reg, value) != ERROR_OK)
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{
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ERROR("BUG: error scheduling etm register write");
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exit(-1);
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}
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buf_set_u32(reg->value, 0, reg->size, value);
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reg->valid = 1;
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reg->dirty = 0;
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return ERROR_OK;
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}
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int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
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{
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etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
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if (jtag_execute_queue() != ERROR_OK)
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{
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ERROR("register write failed");
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exit(-1);
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}
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return ERROR_OK;
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}
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int etb_write_reg(reg_t *reg, u32 value)
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{
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etb_reg_t *etb_reg = reg->arch_info;
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u8 reg_addr = etb_reg->addr & 0x7f;
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scan_field_t fields[3];
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DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
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jtag_add_end_state(TAP_RTI);
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etb_scann(etb_reg->etb, 0x0);
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etb_set_instr(etb_reg->etb, 0xc);
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fields[0].device = etb_reg->etb->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = malloc(4);
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buf_set_u32(fields[0].out_value, 0, 32, value);
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fields[0].out_mask = NULL;
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fields[0].in_value = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = etb_reg->etb->chain_pos;
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fields[1].num_bits = 7;
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fields[1].out_value = malloc(1);
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = etb_reg->etb->chain_pos;
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fields[2].num_bits = 1;
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fields[2].out_value = malloc(1);
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buf_set_u32(fields[2].out_value, 0, 1, 1);
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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free(fields[0].out_value);
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free(fields[1].out_value);
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free(fields[2].out_value);
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return ERROR_OK;
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}
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int etb_store_reg(reg_t *reg)
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{
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return etb_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
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}
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