5df5e89cf3
The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.
This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TRAILING_WHITESPACE --fix-inplace -f {} \;
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5616
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
142 lines
5.5 KiB
INI
142 lines
5.5 KiB
INI
################################################################################
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# Olimex SAM9-L9260 Development Board
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#
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# http://www.olimex.com/dev/sam9-L9260.html
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#
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# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
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# PMC configured for external 18.432 MHz crystal
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#
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# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
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# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
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# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
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#
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################################################################################
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source [find target/at91sam9260.cfg]
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# NTRST_E jumper is enabled by default, so we don't need to override the reset
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# config.
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#reset_config srst_only
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$_TARGETNAME configure -event reset-start {
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# At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if
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# RCLK is not supported.
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jtag_rclk 5
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halt
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# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
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# be enabled... use physical address.
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mww phys 0xfffffd08 0xa5000501
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}
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$_TARGETNAME configure -event reset-init {
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mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
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##
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# Clock configuration for 99.328 MHz main clock.
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##
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echo "Setting up clock"
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mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
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sleep 20 ;# wait 20 ms (need 15.6 ms for startup)
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mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
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sleep 10 ;# wait 10 ms
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mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
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sleep 20 ;# wait 20 ms (need 1.9 ms for startup)
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mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
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sleep 10 ;# wait 10 ms
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mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
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# Increase JTAG speed to 6 MHz if RCLK is not supported.
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jtag_rclk 6000
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arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
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##
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# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
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##
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echo "Configuring SDRAM"
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mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
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mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
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mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
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mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us
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##
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# NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
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##
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echo "Configuring NAND flash"
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mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
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mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
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mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
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mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
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mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
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mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
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mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
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mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
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mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
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mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
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mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
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# 3 TDF cycles, no optimization
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mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
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mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
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nand probe at91sam9260.flash
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##
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# Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
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##
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echo "Setting up dataflash"
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mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
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# 2(SPI0_SPCK), and 11(SPI0_NPCS1)
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mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
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mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
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mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
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mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
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mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
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mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
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mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
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# 250ns delay before SPCK, 250ns b/n tx
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mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
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mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
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}
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nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
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at91sam9 cle 0 22
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at91sam9 ale 0 21
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at91sam9 rdy_busy 0 0xfffff800 13
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at91sam9 ce 0 0xfffff800 14
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