150 lines
4.9 KiB
C
150 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2015 by Uwe Bonnes *
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* bon@elektron.ikp.physik.tu-darmstadt.de *
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***************************************************************************/
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#ifndef OPENOCD_FLASH_NOR_STM32L4X
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#define OPENOCD_FLASH_NOR_STM32L4X
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/* IMPORTANT: this file is included by stm32l4x driver and flashloader,
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* so please when changing this file, do not forget to check the flashloader */
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/* FIXME: #include "helper/bits.h" cause build errors when compiling
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* the flashloader, for now just redefine the needed 'BIT 'macro */
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#ifndef BIT
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#define BIT(nr) (1UL << (nr))
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#endif
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/* FLASH_CR register bits */
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#define FLASH_PG BIT(0)
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#define FLASH_PER BIT(1)
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#define FLASH_MER1 BIT(2)
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#define FLASH_PAGE_SHIFT 3
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#define FLASH_BKER BIT(11)
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#define FLASH_BKER_G0 BIT(13)
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#define FLASH_MER2 BIT(15)
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#define FLASH_STRT BIT(16)
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#define FLASH_OPTSTRT BIT(17)
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#define FLASH_EOPIE BIT(24)
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#define FLASH_ERRIE BIT(25)
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#define FLASH_OBL_LAUNCH BIT(27)
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#define FLASH_OPTLOCK BIT(30)
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#define FLASH_LOCK BIT(31)
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/* FLASH_SR register bits */
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#define FLASH_BSY BIT(16)
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#define FLASH_BSY2 BIT(17)
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/* Fast programming not used => related errors not used*/
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#define FLASH_PGSERR BIT(7) /* Programming sequence error */
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#define FLASH_SIZERR BIT(6) /* Size error */
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#define FLASH_PGAERR BIT(5) /* Programming alignment error */
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#define FLASH_WRPERR BIT(4) /* Write protection error */
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#define FLASH_PROGERR BIT(3) /* Programming error */
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#define FLASH_OPERR BIT(1) /* Operation error */
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#define FLASH_EOP BIT(0) /* End of operation */
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#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
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FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
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/* register unlock keys */
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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/* option register unlock key */
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#define OPTKEY1 0x08192A3B
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#define OPTKEY2 0x4C5D6E7F
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/* FLASH_OPTR register bits */
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#define FLASH_RDP_MASK 0xFF
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#define FLASH_G0_DUAL_BANK BIT(21)
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#define FLASH_G4_DUAL_BANK BIT(22)
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#define FLASH_L4_DUAL_BANK BIT(21)
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#define FLASH_L4R_DBANK BIT(22)
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#define FLASH_LRR_DB1M BIT(21)
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#define FLASH_L5_DBANK BIT(22)
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#define FLASH_L5_DB256 BIT(21)
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#define FLASH_U5_DUALBANK BIT(21)
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#define FLASH_TZEN BIT(31)
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/* FLASH secure block based bank 1/2 register offsets */
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#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
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#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
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#define FLASH_SECBB_SECURE 0xFFFFFFFF
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#define FLASH_SECBB_NON_SECURE 0
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/* IDCODE register possible addresses */
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#define DBGMCU_IDCODE_G0 0x40015800
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#define DBGMCU_IDCODE_L4_G4 0xE0042000
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#define DBGMCU_IDCODE_L5 0xE0044000
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#define UID64_DEVNUM 0x1FFF7580
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#define UID64_IDS 0x1FFF7584
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#define UID64_IDS_STM32WL 0x0080E115
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/* Supported device IDs */
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#define DEVID_STM32L47_L48XX 0x415
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#define DEVID_STM32L43_L44XX 0x435
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#define DEVID_STM32G05_G06XX 0x456
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#define DEVID_STM32G07_G08XX 0x460
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#define DEVID_STM32L49_L4AXX 0x461
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#define DEVID_STM32L45_L46XX 0x462
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#define DEVID_STM32L41_L42XX 0x464
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#define DEVID_STM32G03_G04XX 0x466
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#define DEVID_STM32G0B_G0CXX 0x467
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#define DEVID_STM32G43_G44XX 0x468
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#define DEVID_STM32G47_G48XX 0x469
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#define DEVID_STM32L4R_L4SXX 0x470
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#define DEVID_STM32L4P_L4QXX 0x471
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#define DEVID_STM32L55_L56XX 0x472
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#define DEVID_STM32G49_G4AXX 0x479
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#define DEVID_STM32U57_U58XX 0x482
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#define DEVID_STM32WB1XX 0x494
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#define DEVID_STM32WB5XX 0x495
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#define DEVID_STM32WB3XX 0x496
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#define DEVID_STM32WLE_WL5XX 0x497
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/* known Flash base addresses */
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#define STM32_FLASH_BANK_BASE 0x08000000
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#define STM32_FLASH_S_BANK_BASE 0x0C000000
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/* offset between non-secure and secure flash registers */
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#define STM32L5_REGS_SEC_OFFSET 0x10000000
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/* 100 bytes as loader stack should be large enough for the loader to operate */
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#define LDR_STACK_SIZE 100
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struct stm32l4_work_area {
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struct stm32l4_loader_params {
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uint32_t flash_sr_addr;
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uint32_t flash_cr_addr;
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uint32_t flash_word_size;
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uint32_t flash_sr_bsy_mask;
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} params;
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uint8_t stack[LDR_STACK_SIZE];
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struct flash_async_algorithm_circbuf {
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/* note: stm32l4_work_area struct is shared between the loader
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* and stm32l4x flash driver.
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*
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* '*wp' and '*rp' pointers' size is 4 bytes each since stm32l4x
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* devices have 32-bit processors.
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* however when used in openocd code, their size depends on the host
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* if the host is 32-bit, then the size is 4 bytes each.
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* if the host is 64-bit, then the size is 8 bytes each.
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* to avoid this size difference, change their types depending on the
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* usage (pointers for the loader, and 32-bit integers in openocd code).
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*/
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#ifdef OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X
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uint8_t *wp;
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uint8_t *rp;
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#else
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uint32_t wp;
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uint32_t rp;
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#endif /* OPENOCD_CONTRIB_LOADERS_FLASH_STM32_STM32L4X */
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} fifo;
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};
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#endif
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