45 lines
1.7 KiB
INI
45 lines
1.7 KiB
INI
source [find target/atheros_ar9331.cfg]
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proc ar9331_25mhz_pll_init {} {
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mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
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mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
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mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
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;# OUTDIV | REFDIV | DIV_INT
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mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
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;# (disabled?)
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mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
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mww 0xb8050008 0x00008000 ;# remove bypass;
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;# AHB_POST_DIV - ratio 2
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}
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proc ar9331_ddr1_init {} {
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mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
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mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb800000c 0x2 ;# Extended mode register value.
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;# default 0x2 - Reset to weak driver, DLL on
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mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x33 ;# mode reg: remove some bit?
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
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mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
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;# DQ[7:0], DQS_0
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mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
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;# DQ[15:8], DQS_1.
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mww 0xb8000018 0xff ;# DDR read and capture bit mask.
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;# Each bit represents a cycle of valid data.
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}
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$TARGETNAME configure -event reset-init {
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ar9331_25mhz_pll_init
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sleep 1
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ar9331_ddr1_init
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}
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set ram_boot_address 0xa0000000
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$TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
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