d265c219b9
Someday revisit various issues: Tempest parts support writing more than one word at a time; for some target firmware it might be necessary to save and restore flash IRQ configuration. (The safest policy is likely to always reset after flash updates.) Plus swap some undesirable TAB characters with SPACE. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
108 lines
3.3 KiB
C
108 lines
3.3 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef STELLARIS_FLASH_H
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#define STELLARIS_FLASH_H
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struct stellaris_flash_bank
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{
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/* chip id register */
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uint32_t did0;
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uint32_t did1;
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uint32_t dc0;
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uint32_t dc1;
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char * target_name;
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uint32_t sramsiz;
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uint32_t flshsz;
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/* flash geometry */
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uint32_t num_pages;
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uint32_t pagesize;
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uint32_t pages_in_lockregion;
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/* nv memory bits */
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uint16_t num_lockbits;
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/* main clock status */
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uint32_t rcc;
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uint32_t rcc2;
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uint8_t mck_valid;
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uint8_t xtal_mask;
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uint32_t iosc_freq;
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uint32_t mck_freq;
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const char *iosc_desc;
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const char *mck_desc;
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};
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/* STELLARIS control registers */
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#define SCB_BASE 0x400FE000
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#define DID0 0x000
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#define DID1 0x004
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#define DC0 0x008
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#define DC1 0x010
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#define DC2 0x014
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#define DC3 0x018
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#define DC4 0x01C
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#define RIS 0x050
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#define RCC 0x060
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#define PLLCFG 0x064
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#define RCC2 0x070
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#define NVMSTAT 0x1a0
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/* "legacy" flash memory protection registers (64KB max) */
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#define FMPRE 0x130
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#define FMPPE 0x134
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/* new flash memory protection registers (for more than 64KB) */
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#define FMPRE0 0x200 /* PRE1 = PRE0 + 4, etc */
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#define FMPPE0 0x400 /* PPE1 = PPE0 + 4, etc */
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#define USECRL 0x140
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#define FLASH_CONTROL_BASE 0x400FD000
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#define FLASH_FMA (FLASH_CONTROL_BASE | 0x000)
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#define FLASH_FMD (FLASH_CONTROL_BASE | 0x004)
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#define FLASH_FMC (FLASH_CONTROL_BASE | 0x008)
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#define FLASH_CRIS (FLASH_CONTROL_BASE | 0x00C)
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#define FLASH_CIM (FLASH_CONTROL_BASE | 0x010)
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#define FLASH_MISC (FLASH_CONTROL_BASE | 0x014)
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#define AMISC 1
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#define PMISC 2
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#define AMASK 1
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#define PMASK 2
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/* Flash Controller Command bits */
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#define FMC_WRKEY (0xA442 << 16)
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#define FMC_COMT (1 << 3)
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#define FMC_MERASE (1 << 2)
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#define FMC_ERASE (1 << 1)
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#define FMC_WRITE (1 << 0)
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/* STELLARIS constants */
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/* values to write in FMA to commit write-"once" values */
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#define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */
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#define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */
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#endif /* STELLARIS_H */
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