472 lines
11 KiB
Plaintext
472 lines
11 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Copyright (C) 2008 Lou Deluxe
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# lou.openocd012@fixit.nospammail.net
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#
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m4_divert(`-1')
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m4_dnl Setup and hold times depend on SHIFTER_PRESCALER
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m4_define(`SETUP_DELAY_CYCLES', m4_eval(`('SHIFTER_PRESCALER` + 1) / 2'))
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m4_define(`HOLD_DELAY_CYCLES', m4_eval(`'SHIFTER_PRESCALER` / 2'))
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m4_dnl Some macros to make nybble handling a little easier
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m4_define(`m4_high_nybble', `m4_eval(`(($1) >> 4) & 0xf')')
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m4_define(`m4_low_nybble', `m4_eval(`($1) & 0xf')')
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m4_dnl A macro to generate a number of NOPs depending on the argument
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m4_define(`m4_0_to_5_nops', `m4_ifelse(m4_eval(`($1) >= 1'), 1, ` NOP
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'm4_ifelse(m4_eval(`($1) >= 2'), 1, ` NOP
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'm4_ifelse(m4_eval(`($1) >= 3'), 1, ` NOP
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'm4_ifelse(m4_eval(`($1) >= 4'), 1, ` NOP
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'm4_ifelse(m4_eval(`($1) >= 5'), 1, ` NOP
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')))))')
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m4_dnl Some macros to facilitate bit-banging delays.
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m4_dnl There are 3 of them. One for self-contained delays, and two for those which must be split between setup and loop to keep from disturbing A at delay time.
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m4_dnl The argument passed to any of them is the number of cycles which the delay should consume.
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m4_dnl This one is self-contained.
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m4_define(`m4_delay',
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`; delay (m4_eval($1) cycles)'
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`m4_ifelse(m4_eval(`('$1`) < 6'), 1,
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m4_0_to_5_nops($1)
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,
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m4_ifelse(m4_eval(`(('$1`) - 3) % 2'), 1, ` NOP')
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A.H = m4_high_nybble(`(('$1`) - 3) / 2')
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A.L = m4_low_nybble(`(('$1`) - 3) / 2')
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Y = A
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DECY
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JP -1
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)')
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m4_dnl These are the setup and loop parts of the split delay.
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m4_dnl The argument passed to both must match for the result to make sense.
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m4_dnl The setup does not figure into the delay. It takes 3 cycles when a loop is used and none if nops are used.
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m4_define(`m4_delay_setup',
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`; delay setup (m4_eval($1) cycles)'
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`m4_ifelse(m4_eval(`('$1`) < 6'), 0, ` '
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A.H = m4_high_nybble(`('$1`) / 2')
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A.L = m4_low_nybble(`('$1`) / 2')
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Y = A
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)')
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m4_define(`m4_delay_loop',
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`; delay loop (m4_eval($1) cycles)'
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`m4_ifelse(m4_eval(`('$1`) < 6'), 1,
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m4_0_to_5_nops($1)
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,
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m4_ifelse(m4_eval(`('$1`) % 2'), 1, ` NOP')
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DECY
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JP -1
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)')
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m4_dnl These are utility macros for use with delays. Specifically, there is code below which needs some predictability in code size for relative jumps to reach. The m4_delay macro generates an extra NOP when an even delay is needed, and the m4_delay_loop macro generates an extra NOP when an odd delay is needed. Using this for the argument to the respective macro rounds up the argument so that the extra NOP will not be generated. There is also logic built in to cancel the rounding when the result is small enough that a loop would not be generated.
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m4_define(`m4_delay_loop_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) + 1) / 2 * 2'))')
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m4_define(`m4_delay_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) / 2 * 2) + 1'))')
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m4_divert(`0')m4_dnl
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;------------------------------------------------------------------------------
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:opcode_error
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; This is at address 0x00 in case of empty LUT entries
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STATUS STOP ERROR
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;------------------------------------------------------------------------------
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; Command interpreter at address 0x01 because it is branched to a lot and having it be 0x01 means we can use X for it, which is already used for other purposes which want it to be 1.
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; Assumes X is 1
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; Assumes ADR_BUFFER0 points to the next command byte
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; Stores the current command byte in CMP01
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:command_interpreter
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A = DATA_BUFFER0
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ADR_BUFFER0 += X
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CMP01 = A ; store the current command for later
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EXCHANGE ; put MSN into LSN
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A.H = 0xc ; lookup table at 0x1550 + 0xc0 = 0x1610
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; branch to address in lookup table
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Y = A
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A = <Y>
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BRANCH
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;------------------------------------------------------------------------------
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; LUT for high nybble
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;LUT; c0 opcode_error
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;LUT; c1 opcode_shift_tdi_andor_tms_bytes
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;LUT; c2 opcode_shift_tdi_andor_tms_bytes
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;LUT; c3 opcode_shift_tdi_andor_tms_bytes
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;LUT; c4 opcode_shift_tdo_bytes
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;LUT; c5 opcode_error
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;LUT; c6 opcode_shift_tdio_bytes
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;LUT; c7 opcode_error
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;LUT; c8 opcode_shift_tms_tdi_bit_pair
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;LUT; c9 opcode_shift_tms_bits
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;LUT; ca opcode_error
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;LUT; cb opcode_error
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;LUT; cc opcode_error
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;LUT; cd opcode_error
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;LUT; ce opcode_shift_tdio_bits
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;LUT; cf opcode_stop
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;------------------------------------------------------------------------------
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; USB/buffer handling
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;
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;ENTRY; download entry_download
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opcode_stop:
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opcode_next_buffer:
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; pointer to completion flag
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A.H = 0xf
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A.L = 0xf
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Y = A
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A = OR_MPEG ; buffer indicator from previous iteration
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<Y> = A ; either indicator will have bit 0 set
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BSET 1 ; was buffer 1 previously current?
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; A.H = 0 ; already zero from OR_MPEG
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JP opcode_next_buffer_0
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opcode_next_buffer_1:
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A.L = 0x1 ; ack buffer 0
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BUFFER_MNGT = A
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; A.H = 0x0 ; already zero from BUFFER_MNGT
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A.L = 0x3 ; Input buffer 1 = 0x1850 (0x0300)
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JP +4
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opcode_next_buffer_0:
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A.L = 0x2 ; ack buffer 1
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BUFFER_MNGT = A
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entry_download:
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A = X ; Input buffer 0 = 0x1650 (0x0100)
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ADR_BUFFER01 = A
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OR_MPEG = A ; store for next iteration
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A.L = 0x0
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BUFFER_MNGT = A ; finish acking previous buffer
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Y = A
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ADR_BUFFER00 = A
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ADR_BUFFER11 = A
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A.H = 0x4 ; Output buffer = 0x1590 (0x0040)
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ADR_BUFFER10 = A
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EXCHANGE ; 0x04
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X = A ; for the spin loop below
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; pointer to status in shared memory
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DECY ; setting to 0 above and decrementing here saves a byte
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; wait until a command buffer is available
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A = BUFFER_MNGT ; spin while neither of bits 2 or 3 are set
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CP A<X ; this is slightly faster and smaller than trying to AND and compare the result, and it lets us just use the nybble-swapped 0x40 from the output buffer setup.
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JP -2
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<Y> = A ; update status once done spinning
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; restore X, since we used it
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; A.H = 0 ; high nybble of BUFFER_MNGT will always be 0 the way we use it
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A.L = 1
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X = A
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; go to command interpreter
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BRANCH
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;;------------------------------------------------------------------------------
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;:opcode_stop
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;;
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;
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; ; Ack buffer 0 in download mode
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; A.L = 0x1
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; BUFFER_MNGT = A
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;
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; STATUS STOP
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;------------------------------------------------------------------------------
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:opcode_shift_tdi_andor_tms_bytes
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;
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A = CMP01 ; bits 3..0 contain the number of bytes to shift - 1
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A.H = 0
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Y = A ; loop counter
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A = CMP01
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EXCHANGE
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CMP01 = A ; we're interested in bits in the high nybble
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opcode_shift_tdi_andor_tms_bytes__loop:
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; set tdi to supplied byte or zero
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A = CMP01
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BSET 1
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JP +4
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A.H = 0
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A.L = 0
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JP +3
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A = DATA_BUFFER0
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ADR_BUFFER0 += X
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SHIFT_MPEG = A
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; set tms to supplied byte or zero
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A = CMP01
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BCLR 0
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JP +5
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A = DATA_BUFFER0
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ADR_BUFFER0 += X
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SHIFT_CARD = A
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SHIFT CARD OUT=>PIN0
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; run both shifters as nearly simultaneously as possible
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SHIFT MPEG OUT=>PIN1
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A = CTRL_FCI
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EXCHANGE
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BCLR 3
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JP -3
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DECY
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JP opcode_shift_tdi_andor_tms_bytes__loop
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A = X
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BRANCH
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;------------------------------------------------------------------------------
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:opcode_shift_tdo_bytes
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;
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A = CMP01 ; bits 3..0 contain the number of bytes to shift - 1
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A.H = 0
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Y = A ; loop counter
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opcode_shift_tdo_bytes__loop:
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SHIFT MPEG PIN0=>IN
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A = CTRL_FCI
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EXCHANGE
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BCLR 3
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JP -3
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; put shifted byte into output buffer
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A = SHIFT_MPEG
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DATA_BUFFER1 = A
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ADR_BUFFER1 += X
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DECY
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JP opcode_shift_tdo_bytes__loop
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A = X
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BRANCH
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;------------------------------------------------------------------------------
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:opcode_shift_tdio_bytes
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;
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A = CMP01 ; bits 3..0 contain the number of bytes to shift - 1
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A.H = 0
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CMP10 = A ; byte loop counter
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A.H = opcode_shift_tdio_bytes__sub_return
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A.L = opcode_shift_tdio_bytes__sub_return
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CMP00 = A ; return address
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opcode_shift_tdio_bytes__loop:
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A.H = 0
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A.L = 7
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CMP11 = A ; always use 8 bits
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JP sub_shift_tdio_bits
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opcode_shift_tdio_bytes__sub_return:
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A = CMP10 ; byte loop counter
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CP A=>X
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CLC
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A -= X
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CMP10 = A
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JP opcode_shift_tdio_bytes__loop
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A = X
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;DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
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BRANCH
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;------------------------------------------------------------------------------
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:opcode_shift_tdio_bits
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;
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A = CMP01 ; bits 2..0 contain the number of bits to shift - 1
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A.H = 0
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BCLR 3 ; set TMS=1 if bit 3 was set
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CMP11 = A ; bit loop counter
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A.H = opcode_shift_tdio_bits__sub_return
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A.L = opcode_shift_tdio_bits__sub_return
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CMP00 = A ; return address
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JP sub_shift_tdio_bits
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A.L = 0x1 ; TMS=1
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DR_CARD = A
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JP sub_shift_tdio_bits
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opcode_shift_tdio_bits__sub_return:
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A = X
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;DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
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BRANCH
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;------------------------------------------------------------------------------
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:sub_shift_tdio_bits
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;
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A = DATA_BUFFER0 ; get byte from input buffer
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ADR_BUFFER0 += X
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MASK = A ; put it in MASK where bit routine will use it
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:sub_shift_tdio_bits__loop
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m4_delay_setup(m4_delay_loop_round_up(SETUP_DELAY_CYCLES - 1))
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A = MASK ; shift TDO into and TDI out of MASK via carry
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A += MASK
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MASK = A
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; shifting out TDI
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A.L = 0x2 ; TCK=0, TDI=1
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CP CARRY
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JP +2
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A.L = 0x0 ; TCK=0, TDI=0
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DR_MPEG = A
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m4_delay_loop(m4_delay_loop_round_up(SETUP_DELAY_CYCLES - 1))
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BSET 2 ; TCK high
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DR_MPEG = A
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A = DR_MPEG ; set carry bit to TDO
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CLC
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BCLR 0
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JP +2
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SEC
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m4_delay(HOLD_DELAY_CYCLES - 10)
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A = CMP11 ; bit loop counter
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Y = A ; use Y to avoid corrupting carry bit with subtract
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DECY
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A = Y
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CMP11 = A
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JP :sub_shift_tdio_bits__loop
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; shift last TDO bit into result
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A = MASK
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A += MASK
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DATA_BUFFER1 = A
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ADR_BUFFER1 += X
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A = CMP00 ; return to caller
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BRANCH
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;------------------------------------------------------------------------------
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:opcode_shift_tms_tdi_bit_pair
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;
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; set TMS line manually
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A = CMP01 ; bits 3..0 contain TDI and TMS bits and whether to return TDO
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BSET 0 ; TMS bit
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A.L = 0x1 ; TMS=1
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JP +2
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A.L = 0x0 ; TMS=0
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DR_CARD = A
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; stuff command buffer with bitmap of single TDI bit
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A = CMP01
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BSET 1 ; TDI bit
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A.H = 0x8 ; TDI=1
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JP +2
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A.H = 0x0 ; TDI=0
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ADR_BUFFER0 -= X
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DATA_BUFFER0 = A
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A.H = 0
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A.L = 0
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CMP11 = A ; bit loop counter (only doing one bit)
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A.H = opcode_shift_tms_tdi_bit_pair__sub_return
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A.L = opcode_shift_tms_tdi_bit_pair__sub_return
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CMP00 = A ; return address
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; jump this way due to relative jump range issues
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A.H = sub_shift_tdio_bits
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A.L = sub_shift_tdio_bits
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BRANCH
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opcode_shift_tms_tdi_bit_pair__sub_return:
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A = CMP01
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BSET 3 ; bit says whether to return TDO
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JP +2
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ADR_BUFFER1 -= X ; subroutine returns it, so undo that
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A = X
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DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
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BRANCH
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;------------------------------------------------------------------------------
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:opcode_shift_tms_bits
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;
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A = CMP01 ; bits 3..0 contain the number of bits to shift - 1 (only 1-8 bits is valid... no checking, just improper operation)
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A.H = 0
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CMP11 = A ; bit loop counter
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A = DATA_BUFFER0 ; get byte from input buffer
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ADR_BUFFER0 += X
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MASK = A ; The byte we'll be shifting
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:opcode_shift_tms_bits__loop
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m4_delay_setup(SETUP_DELAY_CYCLES - 1)
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A = MASK ; shift TMS out of MASK via carry
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A += MASK
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MASK = A
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; shifting out TMS
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A.L = 0x1 ; TCK=0, TDI=0, TMS=1
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CP CARRY
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JP +2
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A.L = 0x0 ; TCK=0, TDI=0, TMS=0
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DR_CARD = A
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DR_MPEG = A
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m4_delay_loop(SETUP_DELAY_CYCLES - 1)
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BSET 2 ; TCK high
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DR_MPEG = A
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m4_delay(HOLD_DELAY_CYCLES - 10)
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A = CMP11 ; bit loop counter
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CP A=>X
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CLC
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A -= X
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CMP11 = A
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JP :opcode_shift_tms_bits__loop
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A = X
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DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
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BRANCH
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