f3b1405fdd
This is a remake of http://openocd.zylin.com/1966 originally written by Angus Gratton <gus@projectgus.com> ATSAM4L has a "System Manager Access Port" (SMAP) that holds the CPU in reset if TCK is low when srst (RESET_N) is deasserted. Without this change any use of sysresetreq or srst locks the chip in reset state until power is cycled. A new function smap_reset_deassert is called as reset-deassert-post event handler. It optionally prepares reset vector catch and SMAP reset is released then. Change-Id: Iad736357b0f551725befa2b9e00f3bc54504f3d8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2604 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
28 lines
1020 B
INI
28 lines
1020 B
INI
# script for ATMEL sam4l, a CORTEX-M4 chip
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#
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source [find target/at91sam4XXX.cfg]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
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# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
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# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
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#
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# smap_reset_deassert configures whether we want to run or halt out of reset,
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# then instruct the SMAP to let us out of reset.
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$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
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# SRST (wired to RESET_N) resets debug circuitry
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# srst_pulls_trst is not configured here to avoid an error raised in reset halt
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reset_config srst_gates_jtag
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# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
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# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
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# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
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# but your mileage may vary.
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adapter_khz 50
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# System RC oscillator RCSYS starts in 3 cycles
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adapter_nsrst_delay 0
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