716 lines
24 KiB
C
716 lines
24 KiB
C
/***************************************************************************
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* ESP32-S2 target for OpenOCD *
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* Copyright (C) 2019 Espressif Systems Ltd. *
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* Author: Alexey Gerenkov <alexey@espressif.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "assert.h"
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#include <target/target.h>
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#include <target/target_type.h>
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#include "esp_xtensa.h"
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#include "esp32s2.h"
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/* Overall memory map
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* TODO: read memory configuration from target registers */
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#define ESP32_S2_IROM_MASK_LOW 0x40000000
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#define ESP32_S2_IROM_MASK_HIGH 0x40020000
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#define ESP32_S2_IRAM_LOW 0x40020000
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#define ESP32_S2_IRAM_HIGH 0x40070000
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#define ESP32_S2_DRAM_LOW 0x3ffb0000
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#define ESP32_S2_DRAM_HIGH 0x40000000
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#define ESP32_S2_RTC_IRAM_LOW 0x40070000
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#define ESP32_S2_RTC_IRAM_HIGH 0x40072000
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#define ESP32_S2_RTC_DRAM_LOW 0x3ff9e000
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#define ESP32_S2_RTC_DRAM_HIGH 0x3ffa0000
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#define ESP32_S2_RTC_DATA_LOW 0x50000000
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#define ESP32_S2_RTC_DATA_HIGH 0x50002000
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#define ESP32_S2_EXTRAM_DATA_LOW 0x3f500000
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#define ESP32_S2_EXTRAM_DATA_HIGH 0x3ff80000
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#define ESP32_S2_DR_REG_LOW 0x3f400000
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#define ESP32_S2_DR_REG_HIGH 0x3f4d3FFC
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#define ESP32_S2_SYS_RAM_LOW 0x60000000UL
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#define ESP32_S2_SYS_RAM_HIGH (ESP32_S2_SYS_RAM_LOW + 0x20000000UL)
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/* ESP32-S2 DROM mapping is not contiguous. */
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/* IDF declares this as 0x3F000000..0x3FF80000, but there are peripheral registers mapped to
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* 0x3f400000..0x3f4d3FFC. */
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#define ESP32_S2_DROM0_LOW ESP32_S2_DROM_LOW
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#define ESP32_S2_DROM0_HIGH ESP32_S2_DR_REG_LOW
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#define ESP32_S2_DROM1_LOW ESP32_S2_DR_REG_HIGH
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#define ESP32_S2_DROM1_HIGH ESP32_S2_DROM_HIGH
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/* ESP32 WDT */
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#define ESP32_S2_WDT_WKEY_VALUE 0x50d83aa1
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#define ESP32_S2_TIMG0_BASE 0x3f41F000
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#define ESP32_S2_TIMG1_BASE 0x3f420000
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#define ESP32_S2_TIMGWDT_CFG0_OFF 0x48
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#define ESP32_S2_TIMGWDT_PROTECT_OFF 0x64
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#define ESP32_S2_TIMG0WDT_CFG0 (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
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#define ESP32_S2_TIMG1WDT_CFG0 (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_CFG0_OFF)
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#define ESP32_S2_TIMG0WDT_PROTECT (ESP32_S2_TIMG0_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
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#define ESP32_S2_TIMG1WDT_PROTECT (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
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#define ESP32_S2_RTCCNTL_BASE 0x3f408000
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#define ESP32_S2_RTCWDT_CFG_OFF 0x94
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#define ESP32_S2_RTCWDT_PROTECT_OFF 0xAC
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#define ESP32_S2_SWD_CONF_OFF 0xB0
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#define ESP32_S2_SWD_WPROTECT_OFF 0xB4
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#define ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF 0x8C
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#define ESP32_S2_RTC_CNTL_DIG_PWC_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTC_CNTL_DIG_PWC_REG_OFF)
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#define ESP32_S2_RTCWDT_CFG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)
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#define ESP32_S2_RTCWDT_PROTECT (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)
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#define ESP32_S2_SWD_CONF_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_CONF_OFF)
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#define ESP32_S2_SWD_WPROTECT_REG (ESP32_S2_RTCCNTL_BASE + ESP32_S2_SWD_WPROTECT_OFF)
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#define ESP32_S2_SWD_AUTO_FEED_EN_M BIT(31)
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#define ESP32_S2_SWD_WKEY_VALUE 0x8F1D312AU
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#define ESP32_S2_OPTIONS0 (ESP32_S2_RTCCNTL_BASE + 0x0000)
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#define ESP32_S2_SW_SYS_RST_M 0x80000000
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#define ESP32_S2_SW_SYS_RST_V 0x1
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#define ESP32_S2_SW_SYS_RST_S 31
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#define ESP32_S2_SW_STALL_PROCPU_C0_M ((ESP32_S2_SW_STALL_PROCPU_C0_V) << (ESP32_S2_SW_STALL_PROCPU_C0_S))
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#define ESP32_S2_SW_STALL_PROCPU_C0_V 0x3
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#define ESP32_S2_SW_STALL_PROCPU_C0_S 2
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#define ESP32_S2_SW_CPU_STALL (ESP32_S2_RTCCNTL_BASE + 0x00B8)
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#define ESP32_S2_SW_STALL_PROCPU_C1_M ((ESP32_S2_SW_STALL_PROCPU_C1_V) << (ESP32_S2_SW_STALL_PROCPU_C1_S))
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#define ESP32_S2_SW_STALL_PROCPU_C1_V 0x3FU
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#define ESP32_S2_SW_STALL_PROCPU_C1_S 26
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#define ESP32_S2_CLK_CONF (ESP32_S2_RTCCNTL_BASE + 0x0074)
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#define ESP32_S2_CLK_CONF_DEF 0x1583218
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#define ESP32_S2_STORE4 (ESP32_S2_RTCCNTL_BASE + 0x00BC)
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#define ESP32_S2_STORE5 (ESP32_S2_RTCCNTL_BASE + 0x00C0)
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#define ESP32_S2_DPORT_PMS_OCCUPY_3 0x3F4C10E0
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#define ESP32_S2_TRACEMEM_BLOCK_SZ 0x4000
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#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
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#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
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#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
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/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
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* xtensa-overlay */
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static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
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XT_REG_IDX_PC,
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XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
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XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
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XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
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XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
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XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
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XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
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XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
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XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
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XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
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XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
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XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
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XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
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XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
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XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
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XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
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XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
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XT_REG_IDX_SAR,
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XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
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XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
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ESP32_S2_REG_IDX_GPIOOUT,
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XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
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XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
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XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
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XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
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XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
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XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
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XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
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XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
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XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
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XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
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XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
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XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
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XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
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XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
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XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
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XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
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XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
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XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
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XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
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XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
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XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
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XT_REG_IDX_FAULT_INFO,
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XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
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XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
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XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
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XT_REG_IDX_TRAX_MEMEND,
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XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
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XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
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XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
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};
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static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
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{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
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};
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static const struct xtensa_config esp32s2_xtensa_cfg = {
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.density = true,
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.aregs_num = XT_AREGS_NUM_MAX,
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.windowed = true,
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.coproc = true,
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.miscregs_num = 4,
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.reloc_vec = true,
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.proc_id = true,
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.threadptr = true,
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.user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
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.user_regs = esp32s2_user_regs,
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.fetch_user_regs = xtensa_fetch_user_regs_u32,
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.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
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.gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
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.gdb_regs_mapping = esp32s2_gdb_regs_mapping,
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.irom = {
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.count = 2,
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.regions = {
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{
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.base = ESP32_S2_IROM_LOW,
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.size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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{
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.base = ESP32_S2_IROM_MASK_LOW,
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.size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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}
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},
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.iram = {
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.count = 2,
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.regions = {
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{
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.base = ESP32_S2_IRAM_LOW,
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.size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_RTC_IRAM_LOW,
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.size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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}
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},
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.drom = {
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.count = 2,
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.regions = {
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{
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.base = ESP32_S2_DROM0_LOW,
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.size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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{
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.base = ESP32_S2_DROM1_LOW,
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.size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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}
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},
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.dram = {
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.count = 6,
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.regions = {
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{
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.base = ESP32_S2_DRAM_LOW,
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.size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_RTC_DRAM_LOW,
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.size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_RTC_DATA_LOW,
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.size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_EXTRAM_DATA_LOW,
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.size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_DR_REG_LOW,
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.size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_S2_SYS_RAM_LOW,
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.size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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}
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},
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.exc = {
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.enabled = true,
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},
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.irq = {
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.enabled = true,
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.irq_num = 32,
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},
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.high_irq = {
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.enabled = true,
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.excm_level = 3,
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.nmi_num = 1,
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},
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.tim_irq = {
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.enabled = true,
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.comp_num = 3,
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},
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.debug = {
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.enabled = true,
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.irq_level = 6,
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.ibreaks_num = 2,
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.dbreaks_num = 2,
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.icount_sz = 32,
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},
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.trace = {
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.enabled = true,
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.mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
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},
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};
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struct esp32s2_common {
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struct esp_xtensa_common esp_xtensa;
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};
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static int esp32s2_soc_reset(struct target *target);
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static int esp32s2_disable_wdts(struct target *target);
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static int esp32s2_assert_reset(struct target *target)
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{
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return ERROR_OK;
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}
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static int esp32s2_deassert_reset(struct target *target)
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{
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struct xtensa *xtensa = target_to_xtensa(target);
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LOG_TARGET_DEBUG(target, "begin");
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int res = xtensa_deassert_reset(target);
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if (res != ERROR_OK)
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return res;
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/* restore configured value
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esp32s2_soc_reset() modified it, but can not restore just after SW reset for some reason (???) */
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res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
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if (res != ERROR_OK) {
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LOG_ERROR("Failed to restore smpbreak (%d)!", res);
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return res;
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}
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return ERROR_OK;
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}
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int esp32s2_soft_reset_halt(struct target *target)
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{
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LOG_TARGET_DEBUG(target, "begin");
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/* Reset the SoC first */
|
|
int res = esp32s2_soc_reset(target);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
return xtensa_assert_reset(target);
|
|
}
|
|
|
|
static int esp32s2_set_peri_reg_mask(struct target *target,
|
|
target_addr_t addr,
|
|
uint32_t mask,
|
|
uint32_t val)
|
|
{
|
|
uint32_t reg_val;
|
|
int res = target_read_u32(target, addr, ®_val);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
reg_val = (reg_val & (~mask)) | val;
|
|
res = target_write_u32(target, addr, reg_val);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp32s2_stall_set(struct target *target, bool stall)
|
|
{
|
|
LOG_TARGET_DEBUG(target, "begin");
|
|
|
|
int res = esp32s2_set_peri_reg_mask(target,
|
|
ESP32_S2_SW_CPU_STALL,
|
|
ESP32_S2_SW_STALL_PROCPU_C1_M,
|
|
stall ? 0x21U << ESP32_S2_SW_STALL_PROCPU_C1_S : 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_SW_CPU_STALL (%d)!", res);
|
|
return res;
|
|
}
|
|
res = esp32s2_set_peri_reg_mask(target,
|
|
ESP32_S2_OPTIONS0,
|
|
ESP32_S2_SW_STALL_PROCPU_C0_M,
|
|
stall ? 0x2 << ESP32_S2_SW_STALL_PROCPU_C0_S : 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
|
|
return res;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static inline int esp32s2_stall(struct target *target)
|
|
{
|
|
return esp32s2_stall_set(target, true);
|
|
}
|
|
|
|
static inline int esp32s2_unstall(struct target *target)
|
|
{
|
|
return esp32s2_stall_set(target, false);
|
|
}
|
|
|
|
/* Reset ESP32-S2's peripherals.
|
|
Postconditions: all peripherals except RTC_CNTL are reset, CPU's PC is undefined, PRO CPU is halted, APP CPU is in reset
|
|
How this works:
|
|
0. make sure target is halted; if not, try to halt it; if that fails, try to reset it (via OCD) and then halt
|
|
1. Resets clock related registers
|
|
2. Stalls CPU
|
|
3. trigger SoC reset using RTC_CNTL_SW_SYS_RST bit
|
|
4. CPU is reset and stalled at the first reset vector instruction
|
|
5. wait for the OCD to be reset
|
|
6. halt the target
|
|
7. Unstalls CPU
|
|
8. Disables WDTs and trace memory mapping
|
|
*/
|
|
static int esp32s2_soc_reset(struct target *target)
|
|
{
|
|
int res;
|
|
struct xtensa *xtensa = target_to_xtensa(target);
|
|
|
|
LOG_DEBUG("start");
|
|
|
|
/* In order to write to peripheral registers, target must be halted first */
|
|
if (target->state != TARGET_HALTED) {
|
|
LOG_TARGET_DEBUG(target, "Target not halted before SoC reset, trying to halt it first");
|
|
xtensa_halt(target);
|
|
res = target_wait_state(target, TARGET_HALTED, 1000);
|
|
if (res != ERROR_OK) {
|
|
LOG_TARGET_DEBUG(target, "Couldn't halt target before SoC reset, trying to do reset-halt");
|
|
res = xtensa_assert_reset(target);
|
|
if (res != ERROR_OK) {
|
|
LOG_TARGET_ERROR(
|
|
target,
|
|
"Couldn't halt target before SoC reset! (xtensa_assert_reset returned %d)",
|
|
res);
|
|
return res;
|
|
}
|
|
alive_sleep(10);
|
|
xtensa_poll(target);
|
|
int reset_halt_save = target->reset_halt;
|
|
target->reset_halt = 1;
|
|
res = xtensa_deassert_reset(target);
|
|
target->reset_halt = reset_halt_save;
|
|
if (res != ERROR_OK) {
|
|
LOG_TARGET_ERROR(
|
|
target,
|
|
"Couldn't halt target before SoC reset! (xtensa_deassert_reset returned %d)",
|
|
res);
|
|
return res;
|
|
}
|
|
alive_sleep(10);
|
|
xtensa_poll(target);
|
|
xtensa_halt(target);
|
|
res = target_wait_state(target, TARGET_HALTED, 1000);
|
|
if (res != ERROR_OK) {
|
|
LOG_TARGET_ERROR(target, "Couldn't halt target before SoC reset");
|
|
return res;
|
|
}
|
|
}
|
|
}
|
|
|
|
assert(target->state == TARGET_HALTED);
|
|
|
|
/* Set some clock-related RTC registers to the default values */
|
|
res = target_write_u32(target, ESP32_S2_STORE4, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_STORE4 (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_STORE5, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_STORE5 (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_RTC_CNTL_DIG_PWC_REG, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_RTC_CNTL_DIG_PWC_REG (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_CLK_CONF, ESP32_S2_CLK_CONF_DEF);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_CLK_CONF (%d)!", res);
|
|
return res;
|
|
}
|
|
/* Stall CPU */
|
|
res = esp32s2_stall(target);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
/* enable stall */
|
|
res = xtensa_smpbreak_write(xtensa, OCDDCR_RUNSTALLINEN);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to set smpbreak (%d)!", res);
|
|
return res;
|
|
}
|
|
/* Reset CPU */
|
|
xtensa->suppress_dsr_errors = true;
|
|
res = esp32s2_set_peri_reg_mask(target,
|
|
ESP32_S2_OPTIONS0,
|
|
ESP32_S2_SW_SYS_RST_M,
|
|
1U << ESP32_S2_SW_SYS_RST_S);
|
|
xtensa->suppress_dsr_errors = false;
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);
|
|
return res;
|
|
}
|
|
/* Wait for SoC to reset */
|
|
alive_sleep(100);
|
|
int timeout = 100;
|
|
while (target->state != TARGET_RESET && target->state != TARGET_RUNNING && --timeout > 0) {
|
|
alive_sleep(10);
|
|
xtensa_poll(target);
|
|
}
|
|
if (timeout == 0) {
|
|
LOG_ERROR("Timed out waiting for CPU to be reset, target->state=%d", target->state);
|
|
return ERROR_TARGET_TIMEOUT;
|
|
}
|
|
xtensa_halt(target);
|
|
res = target_wait_state(target, TARGET_HALTED, 1000);
|
|
if (res != ERROR_OK) {
|
|
LOG_TARGET_ERROR(target, "Couldn't halt target before SoC reset");
|
|
return res;
|
|
}
|
|
/* Unstall CPU */
|
|
res = esp32s2_unstall(target);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
/* Disable WDTs */
|
|
res = esp32s2_disable_wdts(target);
|
|
if (res != ERROR_OK)
|
|
return res;
|
|
/* Disable trace memory mapping */
|
|
res = target_write_u32(target, ESP32_S2_DPORT_PMS_OCCUPY_3, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_DPORT_PMS_OCCUPY_3 (%d)!", res);
|
|
return res;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp32s2_disable_wdts(struct target *target)
|
|
{
|
|
/* TIMG1 WDT */
|
|
int res = target_write_u32(target, ESP32_S2_TIMG0WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_TIMG0WDT_PROTECT (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_TIMG0WDT_CFG0, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_TIMG0WDT_CFG0 (%d)!", res);
|
|
return res;
|
|
}
|
|
/* TIMG2 WDT */
|
|
res = target_write_u32(target, ESP32_S2_TIMG1WDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_TIMG1WDT_PROTECT (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_TIMG1WDT_CFG0, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_TIMG1WDT_CFG0 (%d)!", res);
|
|
return res;
|
|
}
|
|
/* RTC WDT */
|
|
res = target_write_u32(target, ESP32_S2_RTCWDT_PROTECT, ESP32_S2_WDT_WKEY_VALUE);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_RTCWDT_PROTECT (%d)!", res);
|
|
return res;
|
|
}
|
|
res = target_write_u32(target, ESP32_S2_RTCWDT_CFG, 0);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_RTCWDT_CFG (%d)!", res);
|
|
return res;
|
|
}
|
|
/* Enable SWD auto-feed */
|
|
res = target_write_u32(target, ESP32_S2_SWD_WPROTECT_REG, ESP32_S2_SWD_WKEY_VALUE);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_SWD_WPROTECT_REG (%d)!", res);
|
|
return res;
|
|
}
|
|
uint32_t swd_conf_reg = 0;
|
|
res = target_read_u32(target, ESP32_S2_SWD_CONF_REG, &swd_conf_reg);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to read ESP32_S2_SWD_CONF_REG (%d)!", res);
|
|
return res;
|
|
}
|
|
swd_conf_reg |= ESP32_S2_SWD_AUTO_FEED_EN_M;
|
|
res = target_write_u32(target, ESP32_S2_SWD_CONF_REG, swd_conf_reg);
|
|
if (res != ERROR_OK) {
|
|
LOG_ERROR("Failed to write ESP32_S2_SWD_CONF_REG (%d)!", res);
|
|
return res;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp32s2_arch_state(struct target *target)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp32s2_on_halt(struct target *target)
|
|
{
|
|
return esp32s2_disable_wdts(target);
|
|
}
|
|
|
|
static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
|
|
{
|
|
int ret = xtensa_step(target, current, address, handle_breakpoints);
|
|
if (ret == ERROR_OK) {
|
|
esp32s2_on_halt(target);
|
|
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int esp32s2_poll(struct target *target)
|
|
{
|
|
enum target_state old_state = target->state;
|
|
int ret = esp_xtensa_poll(target);
|
|
|
|
if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
|
|
/* Call any event callbacks that are applicable */
|
|
if (old_state == TARGET_DEBUG_RUNNING) {
|
|
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
|
|
} else {
|
|
esp32s2_on_halt(target);
|
|
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int esp32s2_virt2phys(struct target *target,
|
|
target_addr_t virtual, target_addr_t *physical)
|
|
{
|
|
*physical = virtual;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int esp32s2_target_init(struct command_context *cmd_ctx, struct target *target)
|
|
{
|
|
return esp_xtensa_target_init(cmd_ctx, target);
|
|
}
|
|
|
|
static const struct xtensa_debug_ops esp32s2_dbg_ops = {
|
|
.queue_enable = xtensa_dm_queue_enable,
|
|
.queue_reg_read = xtensa_dm_queue_reg_read,
|
|
.queue_reg_write = xtensa_dm_queue_reg_write
|
|
};
|
|
|
|
static const struct xtensa_power_ops esp32s2_pwr_ops = {
|
|
.queue_reg_read = xtensa_dm_queue_pwr_reg_read,
|
|
.queue_reg_write = xtensa_dm_queue_pwr_reg_write
|
|
};
|
|
|
|
static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
|
|
{
|
|
struct xtensa_debug_module_config esp32s2_dm_cfg = {
|
|
.dbg_ops = &esp32s2_dbg_ops,
|
|
.pwr_ops = &esp32s2_pwr_ops,
|
|
.tap = target->tap,
|
|
.queue_tdi_idle = NULL,
|
|
.queue_tdi_idle_arg = NULL
|
|
};
|
|
|
|
/* creates xtensa object */
|
|
struct esp32s2_common *esp32 = calloc(1, sizeof(*esp32));
|
|
if (!esp32) {
|
|
LOG_ERROR("Failed to alloc memory for arch info!");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
|
|
if (ret != ERROR_OK) {
|
|
LOG_ERROR("Failed to init arch info!");
|
|
free(esp32);
|
|
return ret;
|
|
}
|
|
|
|
/* Assume running target. If different, the first poll will fix this */
|
|
target->state = TARGET_RUNNING;
|
|
target->debug_reason = DBG_REASON_NOTHALTED;
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const struct command_registration esp32s2_command_handlers[] = {
|
|
{
|
|
.name = "xtensa",
|
|
.mode = COMMAND_ANY,
|
|
.help = "Xtensa commands group",
|
|
.usage = "",
|
|
.chain = xtensa_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
/* Holds methods for Xtensa targets. */
|
|
struct target_type esp32s2_target = {
|
|
.name = "esp32s2",
|
|
|
|
.poll = esp32s2_poll,
|
|
.arch_state = esp32s2_arch_state,
|
|
|
|
.halt = xtensa_halt,
|
|
.resume = xtensa_resume,
|
|
.step = esp32s2_step,
|
|
|
|
.assert_reset = esp32s2_assert_reset,
|
|
.deassert_reset = esp32s2_deassert_reset,
|
|
.soft_reset_halt = esp32s2_soft_reset_halt,
|
|
|
|
.virt2phys = esp32s2_virt2phys,
|
|
.mmu = xtensa_mmu_is_enabled,
|
|
.read_memory = xtensa_read_memory,
|
|
.write_memory = xtensa_write_memory,
|
|
|
|
.read_buffer = xtensa_read_buffer,
|
|
.write_buffer = xtensa_write_buffer,
|
|
|
|
.checksum_memory = xtensa_checksum_memory,
|
|
|
|
.get_gdb_arch = xtensa_get_gdb_arch,
|
|
.get_gdb_reg_list = xtensa_get_gdb_reg_list,
|
|
|
|
.add_breakpoint = esp_xtensa_breakpoint_add,
|
|
.remove_breakpoint = esp_xtensa_breakpoint_remove,
|
|
|
|
.add_watchpoint = xtensa_watchpoint_add,
|
|
.remove_watchpoint = xtensa_watchpoint_remove,
|
|
|
|
.target_create = esp32s2_target_create,
|
|
.init_target = esp32s2_target_init,
|
|
.examine = xtensa_examine,
|
|
.deinit_target = esp_xtensa_target_deinit,
|
|
|
|
.commands = esp32s2_command_handlers,
|
|
};
|