360 lines
11 KiB
C
360 lines
11 KiB
C
/***************************************************************************
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* Generic Xtensa debug module API for OpenOCD *
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* Copyright (C) 2019 Espressif Systems Ltd. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include "xtensa_debug_module.h"
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#define TAPINS_PWRCTL 0x08
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#define TAPINS_PWRSTAT 0x09
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#define TAPINS_NARSEL 0x1C
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#define TAPINS_IDCODE 0x1E
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#define TAPINS_BYPASS 0x1F
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#define TAPINS_PWRCTL_LEN 8
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#define TAPINS_PWRSTAT_LEN 8
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#define TAPINS_NARSEL_ADRLEN 8
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#define TAPINS_NARSEL_DATALEN 32
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#define TAPINS_IDCODE_LEN 32
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#define TAPINS_BYPASS_LEN 1
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static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value)
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{
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struct scan_field field;
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uint8_t t[4] = { 0 };
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memset(&field, 0, sizeof(field));
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field.num_bits = dm->tap->ir_length;
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field.out_value = t;
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buf_set_u32(t, 0, field.num_bits, value);
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jtag_add_ir_scan(dm->tap, &field, TAP_IDLE);
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}
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static void xtensa_dm_add_dr_scan(struct xtensa_debug_module *dm,
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int len,
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const uint8_t *src,
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uint8_t *dest,
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tap_state_t endstate)
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{
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struct scan_field field;
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memset(&field, 0, sizeof(field));
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field.num_bits = len;
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field.out_value = src;
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field.in_value = dest;
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jtag_add_dr_scan(dm->tap, 1, &field, endstate);
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}
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int xtensa_dm_init(struct xtensa_debug_module *dm, const struct xtensa_debug_module_config *cfg)
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{
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if (!dm || !cfg)
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return ERROR_FAIL;
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dm->pwr_ops = cfg->pwr_ops;
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dm->dbg_ops = cfg->dbg_ops;
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dm->tap = cfg->tap;
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dm->queue_tdi_idle = cfg->queue_tdi_idle;
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dm->queue_tdi_idle_arg = cfg->queue_tdi_idle_arg;
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return ERROR_OK;
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}
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int xtensa_dm_queue_enable(struct xtensa_debug_module *dm)
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{
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return dm->dbg_ops->queue_reg_write(dm, NARADR_DCRSET, OCDDCR_ENABLEOCD);
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}
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int xtensa_dm_queue_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *value)
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{
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uint8_t regdata = (reg << 1) | 0;
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uint8_t dummy[4] = { 0, 0, 0, 0 };
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if (reg > NARADR_MAX) {
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LOG_ERROR("Invalid DBG reg ID %d!", reg);
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return ERROR_FAIL;
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}
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xtensa_dm_add_set_ir(dm, TAPINS_NARSEL);
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xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE);
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xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, dummy, value, TAP_IDLE);
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return ERROR_OK;
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}
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int xtensa_dm_queue_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint32_t value)
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{
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uint8_t regdata = (reg << 1) | 1;
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uint8_t valdata[] = { value, value >> 8, value >> 16, value >> 24 };
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if (reg > NARADR_MAX) {
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LOG_ERROR("Invalid DBG reg ID %d!", reg);
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return ERROR_FAIL;
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}
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xtensa_dm_add_set_ir(dm, TAPINS_NARSEL);
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xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_ADRLEN, ®data, NULL, TAP_IDLE);
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xtensa_dm_add_dr_scan(dm, TAPINS_NARSEL_DATALEN, valdata, NULL, TAP_IDLE);
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return ERROR_OK;
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}
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int xtensa_dm_queue_pwr_reg_read(struct xtensa_debug_module *dm, unsigned int reg, uint8_t *data, uint8_t clear)
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{
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uint8_t value_clr = clear;
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uint8_t tap_insn;
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int tap_insn_sz;
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if (reg == DMREG_PWRCTL) {
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tap_insn = TAPINS_PWRCTL;
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tap_insn_sz = TAPINS_PWRCTL_LEN;
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} else if (reg == DMREG_PWRSTAT) {
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tap_insn = TAPINS_PWRSTAT;
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tap_insn_sz = TAPINS_PWRSTAT_LEN;
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} else {
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LOG_ERROR("Invalid PWR reg ID %d!", reg);
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return ERROR_FAIL;
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}
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xtensa_dm_add_set_ir(dm, tap_insn);
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xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value_clr, data, TAP_IDLE);
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return ERROR_OK;
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}
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int xtensa_dm_queue_pwr_reg_write(struct xtensa_debug_module *dm, unsigned int reg, uint8_t data)
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{
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uint8_t value = data;
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uint8_t tap_insn;
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int tap_insn_sz;
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if (reg == DMREG_PWRCTL) {
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tap_insn = TAPINS_PWRCTL;
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tap_insn_sz = TAPINS_PWRCTL_LEN;
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} else if (reg == DMREG_PWRSTAT) {
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tap_insn = TAPINS_PWRSTAT;
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tap_insn_sz = TAPINS_PWRSTAT_LEN;
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} else {
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LOG_ERROR("Invalid PWR reg ID %d!", reg);
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return ERROR_FAIL;
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}
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xtensa_dm_add_set_ir(dm, tap_insn);
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xtensa_dm_add_dr_scan(dm, tap_insn_sz, &value, NULL, TAP_IDLE);
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return ERROR_OK;
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}
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int xtensa_dm_device_id_read(struct xtensa_debug_module *dm)
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{
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uint8_t id_buf[sizeof(uint32_t)];
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dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res != ERROR_OK)
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return res;
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dm->device_id = buf_get_u32(id_buf, 0, 32);
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return ERROR_OK;
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}
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int xtensa_dm_power_status_read(struct xtensa_debug_module *dm, uint32_t clear)
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{
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/* uint8_t id_buf[sizeof(uint32_t)]; */
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/* TODO: JTAG does not work when PWRCTL_JTAGDEBUGUSE is not set.
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* It is set in xtensa_examine(), need to move reading of NARADR_OCDID out of this function */
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/* dm->dbg_ops->queue_reg_read(dm, NARADR_OCDID, id_buf);
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*Read reset state */
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dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stat, clear);
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dm->pwr_ops->queue_reg_read(dm, DMREG_PWRSTAT, &dm->power_status.stath, clear);
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xtensa_dm_queue_tdi_idle(dm);
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return jtag_execute_queue();
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}
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int xtensa_dm_core_status_read(struct xtensa_debug_module *dm)
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{
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uint8_t dsr_buf[sizeof(uint32_t)];
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xtensa_dm_queue_enable(dm);
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dm->dbg_ops->queue_reg_read(dm, NARADR_DSR, dsr_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res != ERROR_OK)
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return res;
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dm->core_status.dsr = buf_get_u32(dsr_buf, 0, 32);
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return res;
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}
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int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bits)
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{
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dm->dbg_ops->queue_reg_write(dm, NARADR_DSR, bits);
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xtensa_dm_queue_tdi_idle(dm);
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return jtag_execute_queue();
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}
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int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
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{
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/*Turn off trace unit so we can start a new trace. */
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dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, 0);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res != ERROR_OK)
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return res;
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/*Set up parameters */
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dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXADDR, 0);
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if (cfg->stopmask != XTENSA_STOPMASK_DISABLED) {
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dm->dbg_ops->queue_reg_write(dm, NARADR_PCMATCHCTRL,
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(cfg->stopmask << PCMATCHCTRL_PCML_SHIFT));
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dm->dbg_ops->queue_reg_write(dm, NARADR_TRIGGERPC, cfg->stoppc);
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}
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dm->dbg_ops->queue_reg_write(dm, NARADR_DELAYCNT, cfg->after);
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/*Options are mostly hardcoded for now. ToDo: make this more configurable. */
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dm->dbg_ops->queue_reg_write(
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dm,
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NARADR_TRAXCTRL,
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TRAXCTRL_TREN |
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((cfg->stopmask != XTENSA_STOPMASK_DISABLED) ? TRAXCTRL_PCMEN : 0) | TRAXCTRL_TMEN |
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(cfg->after_is_words ? 0 : TRAXCTRL_CNTU) | (0 << TRAXCTRL_SMPER_SHIFT) | TRAXCTRL_PTOWS);
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xtensa_dm_queue_tdi_idle(dm);
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return jtag_execute_queue();
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}
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int xtensa_dm_trace_stop(struct xtensa_debug_module *dm, bool pto_enable)
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{
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uint8_t traxctl_buf[sizeof(uint32_t)];
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uint32_t traxctl;
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struct xtensa_trace_status trace_status;
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dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res != ERROR_OK)
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return res;
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traxctl = buf_get_u32(traxctl_buf, 0, 32);
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if (!pto_enable)
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traxctl &= ~(TRAXCTRL_PTOWS | TRAXCTRL_PTOWT);
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dm->dbg_ops->queue_reg_write(dm, NARADR_TRAXCTRL, traxctl | TRAXCTRL_TRSTP);
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xtensa_dm_queue_tdi_idle(dm);
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res = jtag_execute_queue();
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if (res != ERROR_OK)
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return res;
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/*Check current status of trace hardware */
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res = xtensa_dm_trace_status_read(dm, &trace_status);
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if (res != ERROR_OK)
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return res;
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if (trace_status.stat & TRAXSTAT_TRACT) {
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LOG_ERROR("Failed to stop tracing (0x%x)!", trace_status.stat);
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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int xtensa_dm_trace_status_read(struct xtensa_debug_module *dm, struct xtensa_trace_status *status)
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{
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uint8_t traxstat_buf[sizeof(uint32_t)];
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dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXSTAT, traxstat_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res == ERROR_OK && status)
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status->stat = buf_get_u32(traxstat_buf, 0, 32);
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return res;
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}
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int xtensa_dm_trace_config_read(struct xtensa_debug_module *dm, struct xtensa_trace_config *config)
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{
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uint8_t traxctl_buf[sizeof(uint32_t)];
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uint8_t memadrstart_buf[sizeof(uint32_t)];
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uint8_t memadrend_buf[sizeof(uint32_t)];
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uint8_t adr_buf[sizeof(uint32_t)];
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if (!config)
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return ERROR_FAIL;
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dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXCTRL, traxctl_buf);
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dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDRSTART, memadrstart_buf);
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dm->dbg_ops->queue_reg_read(dm, NARADR_MEMADDREND, memadrend_buf);
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dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXADDR, adr_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res == ERROR_OK) {
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config->ctrl = buf_get_u32(traxctl_buf, 0, 32);
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config->memaddr_start = buf_get_u32(memadrstart_buf, 0, 32);
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config->memaddr_end = buf_get_u32(memadrend_buf, 0, 32);
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config->addr = buf_get_u32(adr_buf, 0, 32);
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}
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return res;
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}
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int xtensa_dm_trace_data_read(struct xtensa_debug_module *dm, uint8_t *dest, uint32_t size)
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{
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if (!dest)
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return ERROR_FAIL;
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for (unsigned int i = 0; i < size / 4; i++)
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dm->dbg_ops->queue_reg_read(dm, NARADR_TRAXDATA, &dest[i * 4]);
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xtensa_dm_queue_tdi_idle(dm);
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return jtag_execute_queue();
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}
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int xtensa_dm_perfmon_enable(struct xtensa_debug_module *dm, int counter_id,
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const struct xtensa_perfmon_config *config)
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{
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if (!config)
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return ERROR_FAIL;
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uint8_t pmstat_buf[4];
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uint32_t pmctrl = ((config->tracelevel) << 4) +
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(config->select << 8) +
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(config->mask << 16) +
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(config->kernelcnt << 3);
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/* enable performance monitor */
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dm->dbg_ops->queue_reg_write(dm, NARADR_PMG, 0x1);
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/* reset counter */
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dm->dbg_ops->queue_reg_write(dm, NARADR_PM0 + counter_id, 0);
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dm->dbg_ops->queue_reg_write(dm, NARADR_PMCTRL0 + counter_id, pmctrl);
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dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf);
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xtensa_dm_queue_tdi_idle(dm);
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return jtag_execute_queue();
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}
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int xtensa_dm_perfmon_dump(struct xtensa_debug_module *dm, int counter_id,
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struct xtensa_perfmon_result *out_result)
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{
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uint8_t pmstat_buf[4];
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uint8_t pmcount_buf[4];
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dm->dbg_ops->queue_reg_read(dm, NARADR_PMSTAT0 + counter_id, pmstat_buf);
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dm->dbg_ops->queue_reg_read(dm, NARADR_PM0 + counter_id, pmcount_buf);
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xtensa_dm_queue_tdi_idle(dm);
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int res = jtag_execute_queue();
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if (res == ERROR_OK) {
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uint32_t stat = buf_get_u32(pmstat_buf, 0, 32);
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uint64_t result = buf_get_u32(pmcount_buf, 0, 32);
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/* TODO: if counter # counter_id+1 has 'select' set to 1, use its value as the
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* high 32 bits of the counter. */
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if (out_result) {
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out_result->overflow = ((stat & 1) != 0);
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out_result->value = result;
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}
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}
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return res;
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}
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