faedb14772
This adds the bcm47xx config with the special undocumented trick to put it into standard EJTAG mode from the mystic "LV mode". The RAM setup is not done as it would require considerable efforts without much practical gain. The only issue I noticed so far is that "reset" doesn't actually reset the chip. Unfortunately, it's unclear how to make it work properly with SRST as OpenOCD asserts it in MIPS-specific code so the device will enter LV mode again but the LV tap is already disabled by that time, so it's not possible to send the magic command again. Anyway, this config is more than enough to "recover" any RT-N16 provided the hardware is not damaged. Change-Id: I0894e339763e6d20d1c93341c597382b479d039b Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1849 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
22 lines
845 B
INI
22 lines
845 B
INI
echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed"
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reset_config none
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jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID
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jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu"
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jtag configure $_CHIPNAME-lv.tap -event tap-disable {}
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jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag"
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
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proc switch_lv_to_ejtag {} {
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global _CHIPNAME
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poll 0
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irscan $_CHIPNAME-lv.tap 0x143ff3a
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drscan $_CHIPNAME-lv.tap 32 1
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jtag tapdisable $_CHIPNAME-lv.tap
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poll 1
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}
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