7aade46843
The testee target is usefull for certain non-cpu pass-through situations, for example in the case of a spi flash mapped to the DR of a JTAG tap, as is the case for most FPGAs with SPI flashs behind them. We just manage the RUNNING/RESET/HALTED state in the testee driver to support it being halted which is a requirement for flash banks. Change-Id: I1b4d52c58a1f6bd753e126bfde74dcc5164d7b69 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2840 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> |
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flash | ||
helper | ||
jtag | ||
pld | ||
rtos | ||
server | ||
svf | ||
target | ||
transport | ||
xsvf | ||
hello.c | ||
hello.h | ||
main.c | ||
Makefile.am | ||
openocd.c | ||
openocd.h |