2231da8ec4
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
47 lines
1.5 KiB
INI
47 lines
1.5 KiB
INI
# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs)
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# evaluation boards by Analog Devices (and designs derived from them) use a non-standard 10-pin 0.05" ARM Cortex Debug Connector
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# pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST
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# as a result, a standards-compliant debug pod will only force the processor's debug interface into reset, preventing usage
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# so, a connector adapter must be employed on these boards to isolate or otherwise prevent /TRST from being asserted
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transport select swd
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME ADSP-SC58x
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x3BA02477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -event examine-end {
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global _TARGETNAME
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sc58x_enabledebug $_TARGETNAME
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}
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proc sc58x_enabledebug {target} {
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# Enable debugging functionality by setting relevant bits in the TAPC_DBGCTL register
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# the "phys" option is critical; the OpenOCD Cortex-A target code prevents normal mww when the target is not halted
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# however, it is not possible to halt the target unless these register bits have been set
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$target mww phys 0x31131000 0xFFFF
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}
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