4440bf1fcd
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
151 lines
4.0 KiB
INI
151 lines
4.0 KiB
INI
#
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# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
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# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
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# the same Flash/RAM/MMIO address space.
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#
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source [find target/swj-dp.tcl]
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adapter_khz 1000
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global _CHIPNAME
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME psoc6
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}
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global TARGET
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set TARGET $_CHIPNAME.cpu
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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# Is CM0 Debugging enabled ?
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global _ENABLE_CM0
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if { [info exists ENABLE_CM0] } {
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set _ENABLE_CM0 $ENABLE_CM0
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} else {
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set _ENABLE_CM0 1
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}
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# Is CM4 Debugging enabled ?
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global _ENABLE_CM4
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if { [info exists ENABLE_CM4] } {
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set _ENABLE_CM4 $ENABLE_CM4
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} else {
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set _ENABLE_CM4 1
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}
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global _WORKAREASIZE_CM0
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if { [info exists WORKAREASIZE_CM0] } {
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set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
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} else {
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set _WORKAREASIZE_CM0 0x4000
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}
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global _WORKAREASIZE_CM4
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if { [info exists WORKAREASIZE_CM4] } {
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set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
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} else {
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set _WORKAREASIZE_CM4 0x4000
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}
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global _WORKAREAADDR_CM0
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if { [info exists WORKAREAADDR_CM0] } {
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set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
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} else {
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set _WORKAREAADDR_CM0 0x08000000
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}
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global _WORKAREAADDR_CM4
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if { [info exists WORKAREAADDR_CM4] } {
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set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
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} else {
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set _WORKAREAADDR_CM4 0x08000000
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}
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proc init_reset { mode } {
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global RESET_MODE
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set RESET_MODE $mode
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if {[using_jtag]} {
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jtag arp_init-reset
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}
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}
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# Utility to make 'reset halt' work as reset;halt on a target
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# It does not prevent running code after reset
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proc psoc6_deassert_post { target } {
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# PSoC6 cleared AP registers including TAR during reset
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# Force examine to synchronize OpenOCD target status
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$target arp_examine
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global RESET_MODE
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global TARGET
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if { $RESET_MODE ne "run" } {
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$target arp_poll
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$target arp_poll
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set st [$target curstate]
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if { $st eq "reset" } {
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# we assume running state follows
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# if reset accidentally halts, waiting is useless
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catch { $target arp_waitstate running 100 }
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set st [$target curstate]
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}
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if { $st eq "running" } {
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echo "$target: Ran after reset and before halt..."
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if { $target eq "${TARGET}.cm0" } {
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# Try to cleanly reset whole system
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# and halt the CM0 at entry point
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psoc6 reset_halt
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$target arp_waitstate halted 100
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} else {
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$target arp_halt
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}
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}
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}
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}
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if { $_ENABLE_CM0 } {
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target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
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${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
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flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
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flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0
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flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
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flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
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flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
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flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
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${TARGET}.cm0 cortex_m reset_config sysresetreq
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${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
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}
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if { $_ENABLE_CM4 } {
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target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
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${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
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flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
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flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4
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flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
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flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
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flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
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flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
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${TARGET}.cm4 cortex_m reset_config vectreset
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${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
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}
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if { $_ENABLE_CM0 } {
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# Use CM0+ by default on dual-core devices
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targets ${TARGET}.cm0
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
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}
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