0c8ec7c826
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
75 lines
1.9 KiB
INI
75 lines
1.9 KiB
INI
adapter_khz 1500
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME tms570
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN big
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}
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# TMS570 has an ICEpick-C on which we need the router commands.
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source [find target/icepick.cfg]
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# Main DAP
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# DAP_TAPID should be set before source-ing this file
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
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# ICEpick-C (JTAG route controller)
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# JRC_TAPID should be set before source-ing this file
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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}
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set _JRC_TAPID2 0x0B7B302F
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set _JRC_TAPID3 0x0B95502F
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set _JRC_TAPID4 0x0B97102F
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set _JRC_TAPID5 0x0D8A002F
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set _JRC_TAPID6 0x2B8A002F
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set _JRC_TAPID7 0x2D8A002F
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set _JRC_TAPID8 0x3B8A002F
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set _JRC_TAPID9 0x3D8A002F
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID \
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-expected-id $_JRC_TAPID2 \
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-expected-id $_JRC_TAPID3 \
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-expected-id $_JRC_TAPID4 \
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-expected-id $_JRC_TAPID5 \
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-expected-id $_JRC_TAPID6 \
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-expected-id $_JRC_TAPID7 \
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-expected-id $_JRC_TAPID8 \
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-expected-id $_JRC_TAPID9 \
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-ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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# Cortex-R4 target
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
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-chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
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# TMS570 uses quirky BE-32 mode
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$_TARGETNAME dap ti_be_32_quirks 1
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$_TARGETNAME configure -event gdb-attach {
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cortex_r4 dbginit
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halt
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}
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$_TARGETNAME configure -event "reset-assert" {
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global _CHIPNAME
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# assert warm system reset through ICEPick
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icepick_c_wreset $_CHIPNAME.jrc
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}
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