d4e195ad1b
Some boards might have RCLK omitted from the JTAG connector and if the interface claims support for it, OpenOCD will end up trying to use RCLK while it's actually impossible. This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch. Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1695 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Mathias Küster <kesmtp@freenet.de>
75 lines
2.4 KiB
INI
75 lines
2.4 KiB
INI
# TI OMAP3530
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# http://focus.ti.com/docs/prod/folders/print/omap3530.html
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# Other OMAP3 chips remove DSP and/or the OpenGL support
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME omap3530
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}
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# ICEpick-C ... used to route Cortex, DSP, and more not shown here
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source [find target/icepick.cfg]
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# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
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jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
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# Subsidiary TAP: CoreSight Debug Access Port (DAP)
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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set _DAP_TAPID 0x0b6d602f
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}
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jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
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-expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.dap -event tap-enable \
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"icepick_c_tapenable $_CHIPNAME.jrc 3"
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# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0b7ae02f
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
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-expected-id $_JRC_TAPID
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# GDB target: Cortex-A8, using DAP
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
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# SRAM: 64K at 0x4020.0000; use the first 16K
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$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
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###################
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# the reset sequence is event-driven
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# and kind of finicky...
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# some TCK tycles are required to activate the DEBUG power domain
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jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
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# have the DAP "always" be active
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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proc omap3_dbginit {target} {
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# General Cortex A8 debug initialisation
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cortex_a dbginit
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# Enable DBGU signal for OMAP353x
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$target mww phys 0x5401d030 0x00002000
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}
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# be absolutely certain the JTAG clock will work with the worst-case
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# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
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# OK to speed up *after* PLL and clock tree setup.
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adapter_khz 1000
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$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
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# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
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# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
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# would issue. RST_DPLL3 (4) is a cold reset.
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set PRM_RSTCTRL 0x48307250
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$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
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$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
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