625 lines
17 KiB
C
625 lines
17 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "replacements.h"
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#include "str9x.h"
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#include "flash.h"
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#include "target.h"
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#include "log.h"
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#include "armv4_5.h"
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#include "arm966e.h"
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#include "algorithm.h"
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#include "binarybuffer.h"
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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str9x_mem_layout_t mem_layout_str9bank0[] = {
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{0x00000000, 0x10000, 0x01},
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{0x00010000, 0x10000, 0x02},
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{0x00020000, 0x10000, 0x04},
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{0x00030000, 0x10000, 0x08},
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{0x00040000, 0x10000, 0x10},
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{0x00050000, 0x10000, 0x20},
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{0x00060000, 0x10000, 0x40},
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{0x00070000, 0x10000, 0x80},
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};
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str9x_mem_layout_t mem_layout_str9bank1[] = {
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{0x00000000, 0x02000, 0x100},
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{0x00002000, 0x02000, 0x200},
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{0x00004000, 0x02000, 0x400},
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{0x00006000, 0x02000, 0x800}
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};
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static u32 bank1start = 0x00080000;
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int str9x_register_commands(struct command_context_s *cmd_ctx);
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int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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int str9x_erase(struct flash_bank_s *bank, int first, int last);
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int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
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int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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int str9x_probe(struct flash_bank_s *bank);
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int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int str9x_protect_check(struct flash_bank_s *bank);
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int str9x_erase_check(struct flash_bank_s *bank);
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int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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flash_driver_t str9x_flash =
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{
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.name = "str9x",
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.register_commands = str9x_register_commands,
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.flash_bank_command = str9x_flash_bank_command,
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.erase = str9x_erase,
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.protect = str9x_protect,
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.write = str9x_write,
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.probe = str9x_probe,
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.auto_probe = str9x_probe,
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.erase_check = str9x_erase_check,
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.protect_check = str9x_protect_check,
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.info = str9x_info
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};
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int str9x_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
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register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
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"configure str9 flash controller");
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return ERROR_OK;
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}
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int str9x_build_block_list(struct flash_bank_s *bank)
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{
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str9x_flash_bank_t *str9x_info = bank->driver_priv;
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int i;
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int num_sectors = 0;
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int b0_sectors = 0, b1_sectors = 0;
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switch (bank->size)
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{
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case (256 * 1024):
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b0_sectors = 4;
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break;
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case (512 * 1024):
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b0_sectors = 8;
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break;
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case (32 * 1024):
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b1_sectors = 4;
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bank1start = bank->base;
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break;
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default:
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ERROR("BUG: unknown bank->size encountered");
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exit(-1);
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}
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num_sectors = b0_sectors + b1_sectors;
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bank->num_sectors = num_sectors;
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bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
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str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
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num_sectors = 0;
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for (i = 0; i < b0_sectors; i++)
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{
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bank->sectors[num_sectors].offset = mem_layout_str9bank0[i].sector_start;
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bank->sectors[num_sectors].size = mem_layout_str9bank0[i].sector_size;
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank0[i].sector_bit;
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}
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for (i = 0; i < b1_sectors; i++)
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{
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bank->sectors[num_sectors].offset = mem_layout_str9bank1[i].sector_start;
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bank->sectors[num_sectors].size = mem_layout_str9bank1[i].sector_size;
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank1[i].sector_bit;
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}
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return ERROR_OK;
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}
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/* flash bank str9x <base> <size> 0 0 <target#>
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*/
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int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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{
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str9x_flash_bank_t *str9x_info;
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if (argc < 6)
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{
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WARNING("incomplete flash_bank str9x configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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str9x_info = malloc(sizeof(str9x_flash_bank_t));
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bank->driver_priv = str9x_info;
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str9x_build_block_list(bank);
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str9x_info->write_algorithm = NULL;
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return ERROR_OK;
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}
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int str9x_blank_check(struct flash_bank_s *bank, int first, int last)
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{
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target_t *target = bank->target;
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u8 *buffer;
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int i;
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int nBytes;
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if ((first < 0) || (last > bank->num_sectors))
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return ERROR_FLASH_SECTOR_INVALID;
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if (bank->target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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buffer = malloc(256);
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for (i = first; i <= last; i++)
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{
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bank->sectors[i].is_erased = 1;
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target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
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for (nBytes = 0; nBytes < 256; nBytes++)
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{
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if (buffer[nBytes] != 0xFF)
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{
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bank->sectors[i].is_erased = 0;
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break;
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}
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}
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}
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free(buffer);
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return ERROR_OK;
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}
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int str9x_protect_check(struct flash_bank_s *bank)
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{
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str9x_flash_bank_t *str9x_info = bank->driver_priv;
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target_t *target = bank->target;
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int i;
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u32 adr;
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u16 status;
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if (bank->target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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/* read level one protection */
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adr = bank1start + 0x10;
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target_write_u16(target, adr, 0x90);
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target_read_u16(target, adr, &status);
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target_write_u16(target, adr, 0xFF);
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for (i = 0; i < bank->num_sectors; i++)
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{
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if (status & str9x_info->sector_bits[i])
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bank->sectors[i].is_protected = 1;
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else
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bank->sectors[i].is_protected = 0;
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}
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return ERROR_OK;
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}
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int str9x_erase(struct flash_bank_s *bank, int first, int last)
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{
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target_t *target = bank->target;
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int i;
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u32 adr;
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u8 status;
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for (i = first; i <= last; i++)
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{
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adr = bank->base + bank->sectors[i].offset;
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/* erase sectors */
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target_write_u16(target, adr, 0x20);
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target_write_u16(target, adr, 0xD0);
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/* get status */
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target_write_u16(target, adr, 0x70);
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while (1) {
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target_read_u8(target, adr, &status);
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if( status & 0x80 )
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break;
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usleep(1000);
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}
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/* clear status, also clear read array */
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target_write_u16(target, adr, 0x50);
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/* read array command */
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target_write_u16(target, adr, 0xFF);
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if( status & 0x22 )
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{
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ERROR("error erasing flash bank, status: 0x%x", status);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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for (i = first; i <= last; i++)
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bank->sectors[i].is_erased = 1;
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return ERROR_OK;
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}
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int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
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{
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target_t *target = bank->target;
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int i;
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u32 adr;
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u8 status;
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if (bank->target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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for (i = first; i <= last; i++)
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{
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/* Level One Protection */
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adr = bank->base + bank->sectors[i].offset;
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target_write_u16(target, adr, 0x60);
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if( set )
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target_write_u16(target, adr, 0x01);
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else
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target_write_u16(target, adr, 0xD0);
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/* query status */
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target_read_u8(target, adr, &status);
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}
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return ERROR_OK;
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}
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int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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{
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str9x_flash_bank_t *str9x_info = bank->driver_priv;
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target_t *target = bank->target;
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u32 buffer_size = 8192;
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working_area_t *source;
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u32 address = bank->base + offset;
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reg_param_t reg_params[4];
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armv4_5_algorithm_t armv4_5_info;
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int retval;
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u32 str9x_flash_write_code[] = {
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/* write: */
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0xe3c14003, /* bic r4, r1, #3 */
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0xe3a03040, /* mov r3, #0x40 */
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0xe1c430b0, /* strh r3, [r4, #0] */
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0xe0d030b2, /* ldrh r3, [r0], #2 */
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0xe0c130b2, /* strh r3, [r1], #2 */
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0xe3a03070, /* mov r3, #0x70 */
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0xe1c430b0, /* strh r3, [r4, #0] */
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/* busy: */
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0xe5d43000, /* ldrb r3, [r4, #0] */
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0xe3130080, /* tst r3, #0x80 */
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0x0afffffc, /* beq busy */
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0xe3a05050, /* mov r5, #0x50 */
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0xe1c450b0, /* strh r5, [r4, #0] */
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0xe3a050ff, /* mov r5, #0xFF */
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0xe1c450b0, /* strh r5, [r4, #0] */
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0xe3130012, /* tst r3, #0x12 */
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0x1a000001, /* bne exit */
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0xe2522001, /* subs r2, r2, #1 */
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0x1affffed, /* bne write */
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/* exit: */
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0xeafffffe, /* b exit */
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};
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/* flash write code */
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if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
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{
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WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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};
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target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
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/* memory buffer */
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while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
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{
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buffer_size /= 2;
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if (buffer_size <= 256)
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{
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/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
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if (str9x_info->write_algorithm)
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target_free_working_area(target, str9x_info->write_algorithm);
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WARNING("no large enough working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
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init_reg_param(®_params[3], "r3", 32, PARAM_IN);
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while (count > 0)
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{
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u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
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target_write_buffer(target, source->address, thisrun_count * 2, buffer);
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, address);
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buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
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if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
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{
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target_free_working_area(target, source);
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target_free_working_area(target, str9x_info->write_algorithm);
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ERROR("error executing str9x flash write algorithm");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
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{
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return ERROR_FLASH_OPERATION_FAILED;
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}
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buffer += thisrun_count * 2;
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address += thisrun_count * 2;
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count -= thisrun_count;
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}
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target_free_working_area(target, source);
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target_free_working_area(target, str9x_info->write_algorithm);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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destroy_reg_param(®_params[3]);
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return ERROR_OK;
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}
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int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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{
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target_t *target = bank->target;
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u32 words_remaining = (count / 2);
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u32 bytes_remaining = (count & 0x00000001);
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u32 address = bank->base + offset;
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u32 bytes_written = 0;
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u8 status;
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u32 retval;
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u32 check_address = offset;
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u32 bank_adr;
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int i;
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if (offset & 0x1)
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{
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WARNING("offset 0x%x breaks required 2-byte alignment", offset);
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return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
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}
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for (i = 0; i < bank->num_sectors; i++)
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{
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u32 sec_start = bank->sectors[i].offset;
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u32 sec_end = sec_start + bank->sectors[i].size;
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/* check if destination falls within the current sector */
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if ((check_address >= sec_start) && (check_address < sec_end))
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{
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/* check if destination ends in the current sector */
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if (offset + count < sec_end)
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check_address = offset + count;
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else
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check_address = sec_end;
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}
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}
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if (check_address != offset + count)
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return ERROR_FLASH_DST_OUT_OF_BANK;
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/* multiple half words (2-byte) to be programmed? */
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if (words_remaining > 0)
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{
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/* try using a block write */
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if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
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{
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if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
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{
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/* if block write failed (no sufficient working area),
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* we use normal (slow) single dword accesses */
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WARNING("couldn't use block writes, falling back to single memory accesses");
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}
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else if (retval == ERROR_FLASH_OPERATION_FAILED)
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{
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ERROR("flash writing failed with error code: 0x%x", retval);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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}
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else
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{
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buffer += words_remaining * 2;
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address += words_remaining * 2;
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words_remaining = 0;
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}
|
|
}
|
|
|
|
while (words_remaining > 0)
|
|
{
|
|
bank_adr = address & ~0x03;
|
|
|
|
/* write data command */
|
|
target_write_u16(target, bank_adr, 0x40);
|
|
target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
|
|
|
|
/* get status command */
|
|
target_write_u16(target, bank_adr, 0x70);
|
|
|
|
while (1) {
|
|
target_read_u8(target, bank_adr, &status);
|
|
if( status & 0x80 )
|
|
break;
|
|
usleep(1000);
|
|
}
|
|
|
|
/* clear status reg and read array */
|
|
target_write_u16(target, bank_adr, 0x50);
|
|
target_write_u16(target, bank_adr, 0xFF);
|
|
|
|
if (status & 0x10)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
else if (status & 0x02)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
bytes_written += 2;
|
|
words_remaining--;
|
|
address += 2;
|
|
}
|
|
|
|
if (bytes_remaining)
|
|
{
|
|
u8 last_halfword[2] = {0xff, 0xff};
|
|
int i = 0;
|
|
|
|
while(bytes_remaining > 0)
|
|
{
|
|
last_halfword[i++] = *(buffer + bytes_written);
|
|
bytes_remaining--;
|
|
bytes_written++;
|
|
}
|
|
|
|
bank_adr = address & ~0x03;
|
|
|
|
/* write data comamnd */
|
|
target_write_u16(target, bank_adr, 0x40);
|
|
target->type->write_memory(target, address, 2, 1, last_halfword);
|
|
|
|
/* query status command */
|
|
target_write_u16(target, bank_adr, 0x70);
|
|
|
|
while (1) {
|
|
target_read_u8(target, bank_adr, &status);
|
|
if( status & 0x80 )
|
|
break;
|
|
usleep(1000);
|
|
}
|
|
|
|
/* clear status reg and read array */
|
|
target_write_u16(target, bank_adr, 0x50);
|
|
target_write_u16(target, bank_adr, 0xFF);
|
|
|
|
if (status & 0x10)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
else if (status & 0x02)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int str9x_probe(struct flash_bank_s *bank)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int str9x_erase_check(struct flash_bank_s *bank)
|
|
{
|
|
return str9x_blank_check(bank, 0, bank->num_sectors - 1);
|
|
}
|
|
|
|
int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
|
|
{
|
|
snprintf(buf, buf_size, "str9x flash driver info" );
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
|
{
|
|
str9x_flash_bank_t *str9x_info;
|
|
flash_bank_t *bank;
|
|
target_t *target = NULL;
|
|
|
|
if (argc < 5)
|
|
{
|
|
return ERROR_COMMAND_SYNTAX_ERROR;
|
|
}
|
|
|
|
bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
|
|
if (!bank)
|
|
{
|
|
command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
str9x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
{
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
/* config flash controller */
|
|
target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));
|
|
target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));
|
|
target_write_u32(target, FLASH_BBADR, (strtoul(args[3], NULL, 0) >> 2));
|
|
target_write_u32(target, FLASH_NBBADR, (strtoul(args[4], NULL, 0) >> 2));
|
|
|
|
/* set bit 18 instruction TCM order as per flash programming manual */
|
|
arm966e_write_cp15(target, 62, 0x40000);
|
|
|
|
/* enable flash bank 1 */
|
|
target_write_u32(target, FLASH_CR, 0x18);
|
|
return ERROR_OK;
|
|
}
|