8193f17c3a
Same deal: "register.h" got needlessly included all over the place because of being in a few widely included headers. So take it out of the header files which included it, and put it in files which use it ... reduce needless interdependencies. Also, don't need that extra "types.h" inclusion. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
155 lines
5.9 KiB
C
155 lines
5.9 KiB
C
/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef MIPS32_H
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#define MIPS32_H
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#include "target.h"
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#include "mips32_pracc.h"
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#define MIPS32_COMMON_MAGIC 0xB320B320
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/* offsets into mips32 core register cache */
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enum
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{
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MIPS32_PC = 37,
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MIPS32NUMCOREREGS
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};
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struct mips32_comparator
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{
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int used;
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//int type;
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uint32_t bp_value;
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uint32_t reg_address;
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};
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struct mips32_common
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{
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uint32_t common_magic;
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void *arch_info;
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struct reg_cache *core_cache;
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struct mips_ejtag ejtag_info;
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uint32_t core_regs[MIPS32NUMCOREREGS];
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int bp_scanned;
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int num_inst_bpoints;
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int num_data_bpoints;
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int num_inst_bpoints_avail;
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int num_data_bpoints_avail;
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struct mips32_comparator *inst_break_list;
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struct mips32_comparator *data_break_list;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target *target, int num);
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int (*write_core_reg)(struct target *target, int num);
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};
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struct mips32_core_reg
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{
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uint32_t num;
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struct target *target;
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struct mips32_common *mips32_common;
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};
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#define MIPS32_OP_BEQ 0x04
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#define MIPS32_OP_BNE 0x05
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#define MIPS32_OP_ADDI 0x08
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#define MIPS32_OP_AND 0x24
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#define MIPS32_OP_COP0 0x10
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#define MIPS32_OP_LUI 0x0F
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#define MIPS32_OP_LW 0x23
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#define MIPS32_OP_LBU 0x24
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#define MIPS32_OP_LHU 0x25
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#define MIPS32_OP_MFHI 0x10
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#define MIPS32_OP_MTHI 0x11
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#define MIPS32_OP_MFLO 0x12
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#define MIPS32_OP_MTLO 0x13
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#define MIPS32_OP_SB 0x28
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#define MIPS32_OP_SH 0x29
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#define MIPS32_OP_SW 0x2B
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#define MIPS32_OP_ORI 0x0D
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#define MIPS32_COP0_MF 0x00
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#define MIPS32_COP0_MT 0x04
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#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
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#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
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#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
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#define MIPS32_NOP 0
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#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
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#define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
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#define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
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#define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
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#define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
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#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
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#define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
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#define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
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#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
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#define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
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#define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
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#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
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#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
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#define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
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#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
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/* ejtag specific instructions */
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#define MIPS32_DRET 0x4200001F
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#define MIPS32_SDBBP 0x7000003F
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#define MIPS16_SDBBP 0xE801
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int mips32_arch_state(struct target *target);
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int mips32_init_arch_info(struct target *target,
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struct mips32_common *mips32, struct jtag_tap *tap);
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int mips32_restore_context(struct target *target);
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int mips32_save_context(struct target *target);
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struct reg_cache *mips32_build_reg_cache(struct target *target);
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int mips32_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t entry_point, uint32_t exit_point,
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int timeout_ms, void *arch_info);
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int mips32_configure_break_unit(struct target *target);
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int mips32_enable_interrupts(struct target *target, int enable);
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int mips32_examine(struct target *target);
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int mips32_register_commands(struct command_context *cmd_ctx);
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int mips32_invalidate_core_regs(struct target *target);
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int mips32_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size);
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#endif /*MIPS32_H*/
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