f2b4897773
The device has compatible flash macro with STM32F1 family, reuse stm32f1x driver code. Detect non-ARM target - for simplicy test target type name 'riscv' and the address has 32 bits. In case of RISC-V CPU use simple chunked write algo - async algo cannot be used as the core implemented in this device doesn't allow memory access while running. Change-Id: Ie3886fbd8573652691f91a02335812a7300689f7 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6704 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com> |
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.. | ||
checksum | ||
debug/xscale | ||
erase_check | ||
flash | ||
watchdog | ||
Makefile | ||
README |
Included in these directories are the src to the various ram loaders used within openocd. ** target checksum loaders ** checksum/armv4_5_crc.s : - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code checksum/armv7m_crc.s : - ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code checksum/mips32.s : - MIPS32 checksum loader : see target/mips32.c:mips_crc_code ** target flash loaders ** flash/pic32mx.s : - Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code flash/stellaris.s : - TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code flash/stm32x.s : - ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code flash/str7x.s : - ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code flash/str9x.s : - ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code Spencer Oliver spen@spen-soft.co.uk