700 lines
19 KiB
C
700 lines
19 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "str7x.h"
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#include "armv4_5.h"
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#include "binarybuffer.h"
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#include "algorithm.h"
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struct str7x_mem_layout mem_layout_str7bank0[] = {
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{0x00000000, 0x02000, 0x01},
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{0x00002000, 0x02000, 0x02},
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{0x00004000, 0x02000, 0x04},
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{0x00006000, 0x02000, 0x08},
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{0x00008000, 0x08000, 0x10},
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{0x00010000, 0x10000, 0x20},
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{0x00020000, 0x10000, 0x40},
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{0x00030000, 0x10000, 0x80}
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};
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struct str7x_mem_layout mem_layout_str7bank1[] = {
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{0x00000000, 0x02000, 0x10000},
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{0x00002000, 0x02000, 0x20000}
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};
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static int str7x_get_flash_adr(struct flash_bank *bank, uint32_t reg)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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return (str7x_info->register_base | reg);
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}
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static int str7x_build_block_list(struct flash_bank *bank)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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int i;
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int num_sectors;
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int b0_sectors = 0, b1_sectors = 0;
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switch (bank->size)
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{
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case 16 * 1024:
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b1_sectors = 2;
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break;
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case 64 * 1024:
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b0_sectors = 5;
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break;
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case 128 * 1024:
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b0_sectors = 6;
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break;
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case 256 * 1024:
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b0_sectors = 8;
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break;
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default:
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LOG_ERROR("BUG: unknown bank->size encountered");
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exit(-1);
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}
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num_sectors = b0_sectors + b1_sectors;
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bank->num_sectors = num_sectors;
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bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
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str7x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
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num_sectors = 0;
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for (i = 0; i < b0_sectors; i++)
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{
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bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
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bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
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}
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for (i = 0; i < b1_sectors; i++)
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{
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bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
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bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
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}
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return ERROR_OK;
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}
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/* flash bank str7x <base> <size> 0 0 <target#> <str71_variant>
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*/
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FLASH_BANK_COMMAND_HANDLER(str7x_flash_bank_command)
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{
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struct str7x_flash_bank *str7x_info;
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if (CMD_ARGC < 7)
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{
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LOG_WARNING("incomplete flash_bank str7x configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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str7x_info = malloc(sizeof(struct str7x_flash_bank));
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bank->driver_priv = str7x_info;
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/* set default bits for str71x flash */
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str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA1 | FLASH_BSYA0);
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str7x_info->disable_bit = (1 << 1);
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if (strcmp(CMD_ARGV[6], "STR71x") == 0)
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{
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str7x_info->register_base = 0x40100000;
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}
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else if (strcmp(CMD_ARGV[6], "STR73x") == 0)
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{
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str7x_info->register_base = 0x80100000;
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str7x_info->busy_bits = (FLASH_LOCK | FLASH_BSYA0);
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}
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else if (strcmp(CMD_ARGV[6], "STR75x") == 0)
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{
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str7x_info->register_base = 0x20100000;
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str7x_info->disable_bit = (1 << 0);
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}
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else
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{
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LOG_ERROR("unknown STR7x variant: '%s'", CMD_ARGV[6]);
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free(str7x_info);
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return ERROR_FLASH_BANK_INVALID;
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}
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str7x_build_block_list(bank);
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str7x_info->write_algorithm = NULL;
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return ERROR_OK;
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}
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static uint32_t str7x_status(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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uint32_t retval;
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
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return retval;
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}
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static uint32_t str7x_result(struct flash_bank *bank)
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{
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struct target *target = bank->target;
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uint32_t retval;
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
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return retval;
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}
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static int str7x_protect_check(struct flash_bank *bank)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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struct target *target = bank->target;
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int i;
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uint32_t retval;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
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for (i = 0; i < bank->num_sectors; i++)
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{
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if (retval & str7x_info->sector_bits[i])
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bank->sectors[i].is_protected = 0;
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else
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bank->sectors[i].is_protected = 1;
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}
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return ERROR_OK;
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}
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static int str7x_erase(struct flash_bank *bank, int first, int last)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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struct target *target = bank->target;
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int i;
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uint32_t cmd;
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uint32_t retval;
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uint32_t sectors = 0;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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for (i = first; i <= last; i++)
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{
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sectors |= str7x_info->sector_bits[i];
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}
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LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
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/* clear FLASH_ER register */
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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cmd = FLASH_SER;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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cmd = sectors;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
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cmd = FLASH_SER | FLASH_WMS;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
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alive_sleep(1);
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}
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retval = str7x_result(bank);
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if (retval)
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{
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LOG_ERROR("error erasing flash bank, FLASH_ER: 0x%" PRIx32 "", retval);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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for (i = first; i <= last; i++)
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bank->sectors[i].is_erased = 1;
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return ERROR_OK;
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}
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static int str7x_protect(struct flash_bank *bank, int set, int first, int last)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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struct target *target = bank->target;
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int i;
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uint32_t cmd;
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uint32_t retval;
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uint32_t protect_blocks;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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protect_blocks = 0xFFFFFFFF;
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if (set)
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{
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for (i = first; i <= last; i++)
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protect_blocks &= ~(str7x_info->sector_bits[i]);
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}
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/* clear FLASH_ER register */
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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cmd = FLASH_SPR;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
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cmd = protect_blocks;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
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cmd = FLASH_SPR | FLASH_WMS;
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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while (((retval = str7x_status(bank)) & str7x_info->busy_bits)) {
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alive_sleep(1);
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}
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retval = str7x_result(bank);
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LOG_DEBUG("retval: 0x%8.8" PRIx32 "", retval);
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if (retval & FLASH_ERER)
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return ERROR_FLASH_SECTOR_NOT_ERASED;
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else if (retval & FLASH_WPF)
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return ERROR_FLASH_OPERATION_FAILED;
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return ERROR_OK;
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}
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static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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struct target *target = bank->target;
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uint32_t buffer_size = 8192;
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struct working_area *source;
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uint32_t address = bank->base + offset;
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struct reg_param reg_params[6];
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struct armv4_5_algorithm armv4_5_info;
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int retval = ERROR_OK;
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uint32_t str7x_flash_write_code[] = {
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/* write: */
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0xe3a04201, /* mov r4, #0x10000000 */
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0xe5824000, /* str r4, [r2, #0x0] */
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0xe5821010, /* str r1, [r2, #0x10] */
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0xe4904004, /* ldr r4, [r0], #4 */
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0xe5824008, /* str r4, [r2, #0x8] */
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0xe4904004, /* ldr r4, [r0], #4 */
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0xe582400c, /* str r4, [r2, #0xc] */
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0xe3a04209, /* mov r4, #0x90000000 */
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0xe5824000, /* str r4, [r2, #0x0] */
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/* busy: */
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0xe5924000, /* ldr r4, [r2, #0x0] */
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0xe1140005, /* tst r4, r5 */
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0x1afffffc, /* bne busy */
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0xe5924014, /* ldr r4, [r2, #0x14] */
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0xe31400ff, /* tst r4, #0xff */
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0x03140c01, /* tsteq r4, #0x100 */
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0x1a000002, /* bne exit */
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0xe2811008, /* add r1, r1, #0x8 */
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0xe2533001, /* subs r3, r3, #1 */
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0x1affffec, /* bne write */
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/* exit: */
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0xeafffffe, /* b exit */
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};
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/* flash write code */
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if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
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{
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LOG_WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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};
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target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, (uint8_t*)str7x_flash_write_code);
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/* memory buffer */
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while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
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{
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buffer_size /= 2;
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if (buffer_size <= 256)
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{
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/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
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if (str7x_info->write_algorithm)
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target_free_working_area(target, str7x_info->write_algorithm);
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LOG_WARNING("no large enough working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
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init_reg_param(®_params[4], "r4", 32, PARAM_IN);
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init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
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while (count > 0)
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{
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uint32_t thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
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target_write_buffer(target, source->address, thisrun_count * 8, buffer);
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buf_set_u32(reg_params[0].value, 0, 32, source->address);
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buf_set_u32(reg_params[1].value, 0, 32, address);
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buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
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buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
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buf_set_u32(reg_params[5].value, 0, 32, str7x_info->busy_bits);
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if ((retval = target_run_algorithm(target, 0, NULL, 6, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
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{
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LOG_ERROR("error executing str7x flash write algorithm");
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
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{
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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buffer += thisrun_count * 8;
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address += thisrun_count * 8;
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count -= thisrun_count;
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}
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target_free_working_area(target, source);
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target_free_working_area(target, str7x_info->write_algorithm);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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destroy_reg_param(®_params[3]);
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destroy_reg_param(®_params[4]);
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destroy_reg_param(®_params[5]);
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return retval;
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}
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static int str7x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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struct str7x_flash_bank *str7x_info = bank->driver_priv;
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uint32_t dwords_remaining = (count / 8);
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uint32_t bytes_remaining = (count & 0x00000007);
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uint32_t address = bank->base + offset;
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uint32_t bytes_written = 0;
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uint32_t cmd;
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int retval;
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uint32_t check_address = offset;
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int i;
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if (bank->target->state != TARGET_HALTED)
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{
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (offset & 0x7)
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{
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LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset);
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return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
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}
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for (i = 0; i < bank->num_sectors; i++)
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{
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uint32_t sec_start = bank->sectors[i].offset;
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uint32_t sec_end = sec_start + bank->sectors[i].size;
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/* check if destination falls within the current sector */
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if ((check_address >= sec_start) && (check_address < sec_end))
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{
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/* check if destination ends in the current sector */
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if (offset + count < sec_end)
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check_address = offset + count;
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else
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check_address = sec_end;
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}
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}
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if (check_address != offset + count)
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return ERROR_FLASH_DST_OUT_OF_BANK;
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/* clear FLASH_ER register */
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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/* multiple dwords (8-byte) to be programmed? */
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if (dwords_remaining > 0)
|
|
{
|
|
/* try using a block write */
|
|
if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
|
|
{
|
|
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
|
{
|
|
/* if block write failed (no sufficient working area),
|
|
* we use normal (slow) single dword accesses */
|
|
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
|
}
|
|
else if (retval == ERROR_FLASH_OPERATION_FAILED)
|
|
{
|
|
/* if an error occured, we examine the reason, and quit */
|
|
retval = str7x_result(bank);
|
|
|
|
LOG_ERROR("flash writing failed with error code: 0x%x", retval);
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
buffer += dwords_remaining * 8;
|
|
address += dwords_remaining * 8;
|
|
dwords_remaining = 0;
|
|
}
|
|
}
|
|
|
|
while (dwords_remaining > 0)
|
|
{
|
|
/* command */
|
|
cmd = FLASH_DWPG;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
|
|
|
/* address */
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
|
|
|
|
/* data word 1 */
|
|
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
|
|
bytes_written += 4;
|
|
|
|
/* data word 2 */
|
|
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
|
|
bytes_written += 4;
|
|
|
|
/* start programming cycle */
|
|
cmd = FLASH_DWPG | FLASH_WMS;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
|
|
|
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
|
|
{
|
|
alive_sleep(1);
|
|
}
|
|
|
|
retval = str7x_result(bank);
|
|
|
|
if (retval & FLASH_PGER)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
else if (retval & FLASH_WPF)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
dwords_remaining--;
|
|
address += 8;
|
|
}
|
|
|
|
if (bytes_remaining)
|
|
{
|
|
uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
|
int i = 0;
|
|
|
|
while (bytes_remaining > 0)
|
|
{
|
|
last_dword[i++] = *(buffer + bytes_written);
|
|
bytes_remaining--;
|
|
bytes_written++;
|
|
}
|
|
|
|
/* command */
|
|
cmd = FLASH_DWPG;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
|
|
|
/* address */
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
|
|
|
|
/* data word 1 */
|
|
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
|
|
bytes_written += 4;
|
|
|
|
/* data word 2 */
|
|
target_write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
|
|
bytes_written += 4;
|
|
|
|
/* start programming cycle */
|
|
cmd = FLASH_DWPG | FLASH_WMS;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
|
|
|
while (((retval = str7x_status(bank)) & str7x_info->busy_bits))
|
|
{
|
|
alive_sleep(1);
|
|
}
|
|
|
|
retval = str7x_result(bank);
|
|
|
|
if (retval & FLASH_PGER)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
else if (retval & FLASH_WPF)
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int str7x_probe(struct flash_bank *bank)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
|
|
#if 0
|
|
COMMAND_HANDLER(str7x_handle_part_id_command)
|
|
{
|
|
return ERROR_OK;
|
|
}
|
|
#endif
|
|
|
|
static int str7x_info(struct flash_bank *bank, char *buf, int buf_size)
|
|
{
|
|
snprintf(buf, buf_size, "str7x flash driver info");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(str7x_handle_disable_jtag_command)
|
|
{
|
|
struct target *target = NULL;
|
|
struct str7x_flash_bank *str7x_info = NULL;
|
|
|
|
uint32_t flash_cmd;
|
|
uint16_t ProtectionLevel = 0;
|
|
uint16_t ProtectionRegs;
|
|
|
|
if (CMD_ARGC < 1)
|
|
{
|
|
command_print(CMD_CTX, "str7x disable_jtag <bank>");
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_bank *bank;
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
|
if (ERROR_OK != retval)
|
|
return retval;
|
|
|
|
str7x_info = bank->driver_priv;
|
|
|
|
target = bank->target;
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
LOG_ERROR("Target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
/* first we get protection status */
|
|
uint32_t reg;
|
|
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR0), ®);
|
|
|
|
if (!(reg & str7x_info->disable_bit))
|
|
{
|
|
ProtectionLevel = 1;
|
|
}
|
|
|
|
target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVAPR1), ®);
|
|
ProtectionRegs = ~(reg >> 16);
|
|
|
|
while (((ProtectionRegs) != 0) && (ProtectionLevel < 16))
|
|
{
|
|
ProtectionRegs >>= 1;
|
|
ProtectionLevel++;
|
|
}
|
|
|
|
if (ProtectionLevel == 0)
|
|
{
|
|
flash_cmd = FLASH_SPR;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFB8);
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), 0xFFFFFFFD);
|
|
flash_cmd = FLASH_SPR | FLASH_WMS;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
|
|
}
|
|
else
|
|
{
|
|
flash_cmd = FLASH_SPR;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1 << (15 + ProtectionLevel)));
|
|
flash_cmd = FLASH_SPR | FLASH_WMS;
|
|
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int str7x_register_commands(struct command_context *cmd_ctx)
|
|
{
|
|
struct command *str7x_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "str7x",
|
|
NULL, COMMAND_ANY, "str7x flash specific commands");
|
|
|
|
COMMAND_REGISTER(cmd_ctx, str7x_cmd, "disable_jtag",
|
|
str7x_handle_disable_jtag_command, COMMAND_EXEC,
|
|
"disable jtag access");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
struct flash_driver str7x_flash = {
|
|
.name = "str7x",
|
|
.register_commands = &str7x_register_commands,
|
|
.flash_bank_command = &str7x_flash_bank_command,
|
|
.erase = &str7x_erase,
|
|
.protect = &str7x_protect,
|
|
.write = &str7x_write,
|
|
.probe = &str7x_probe,
|
|
.auto_probe = &str7x_probe,
|
|
.erase_check = &default_flash_blank_check,
|
|
.protect_check = &str7x_protect_check,
|
|
.info = &str7x_info,
|
|
};
|