Some boards require a slower clock speed because of passive components on the
JTAG/SWD lines. The previous implementation would first try to discover the
chips on the default speed, and only after discovery switch to the requested
adapter_khz speed.
This patch moves the speed change to just before entering the SWD/JTAG mode,
which should alleviate this problem.
Tested on an STLink V2 clone.
Change-Id: I9734452dcc8bb28d6629e64d9a7e32ef92868cf9
Signed-off-by: Frans-Willem Hardijzer <fw@hardijzer.nl>
Reviewed-on: http://openocd.zylin.com/4818
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
89f07325f2