849 lines
26 KiB
C
849 lines
26 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include "config.h"
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#include "arm9tdmi.h"
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#include "arm7_9_common.h"
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#include "register.h"
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#include "target.h"
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#include "armv4_5.h"
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#include "embeddedice.h"
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#include "log.h"
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#include "jtag.h"
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#include "arm_jtag.h"
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#include <stdlib.h>
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#include <string.h>
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#if 0
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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/* cli handling */
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int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
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/* forward declarations */
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int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
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int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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int arm9tdmi_quit();
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/* target function declarations */
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enum target_state arm9tdmi_poll(struct target_s *target);
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int arm9tdmi_halt(target_t *target);
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int arm9tdmi_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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target_type_t arm9tdmi_target =
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{
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.name = "arm9tdmi",
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.poll = arm7_9_poll,
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.arch_state = armv4_5_arch_state,
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.halt = arm7_9_halt,
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.resume = arm7_9_resume,
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.step = arm7_9_step,
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.assert_reset = arm7_9_assert_reset,
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.deassert_reset = arm7_9_deassert_reset,
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.soft_reset_halt = arm7_9_soft_reset_halt,
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.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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.read_memory = arm7_9_read_memory,
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.write_memory = arm7_9_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.add_breakpoint = arm7_9_add_breakpoint,
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.remove_breakpoint = arm7_9_remove_breakpoint,
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.add_watchpoint = arm7_9_add_watchpoint,
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.remove_watchpoint = arm7_9_remove_watchpoint,
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.register_commands = arm9tdmi_register_commands,
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.target_command = arm9tdmi_target_command,
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.init_target = arm9tdmi_init_target,
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.quit = arm9tdmi_quit
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};
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int arm9tdmi_examine_debug_reason(target_t *target)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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/* only check the debug reason if we don't know it already */
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP))
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{
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scan_field_t fields[3];
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u8 databus[4];
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u8 instructionbus[4];
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u8 debug_reason;
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jtag_add_end_state(TAP_PD);
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fields[0].device = arm7_9->jtag_info.chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = NULL;
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fields[0].out_mask = NULL;
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fields[0].in_value = databus;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = arm7_9->jtag_info.chain_pos;
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fields[1].num_bits = 3;
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fields[1].out_value = NULL;
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fields[1].out_mask = NULL;
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fields[1].in_value = &debug_reason;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = arm7_9->jtag_info.chain_pos;
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fields[2].num_bits = 32;
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fields[2].out_value = NULL;
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fields[2].out_mask = NULL;
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fields[2].in_value = instructionbus;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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arm_jtag_scann(&arm7_9->jtag_info, 0x1);
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arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
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jtag_add_dr_scan(3, fields, TAP_PD);
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jtag_execute_queue();
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fields[0].in_value = NULL;
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fields[0].out_value = databus;
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fields[1].in_value = NULL;
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fields[1].out_value = &debug_reason;
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fields[2].in_value = NULL;
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fields[2].out_value = instructionbus;
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jtag_add_dr_scan(3, fields, TAP_PD);
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if (debug_reason & 0x4)
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if (debug_reason & 0x2)
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target->debug_reason = DBG_REASON_WPTANDBKPT;
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else
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target->debug_reason = DBG_REASON_WATCHPOINT;
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else
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target->debug_reason = DBG_REASON_BREAKPOINT;
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}
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return ERROR_OK;
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}
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/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
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int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
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{
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scan_field_t fields[3];
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u8 out_buf[4];
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u8 instr_buf[4];
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u8 sysspeed_buf = 0x0;
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/* prepare buffer */
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buf_set_u32(out_buf, 0, 32, out);
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instr = flip_u32(instr, 32);
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buf_set_u32(instr_buf, 0, 32, instr);
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if (sysspeed)
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buf_set_u32(&sysspeed_buf, 2, 1, 1);
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = out_buf;
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fields[0].out_mask = NULL;
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if (in)
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{
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fields[0].in_value = (u8*)in;
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} else
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{
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fields[0].in_value = NULL;
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}
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 3;
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fields[1].out_value = &sysspeed_buf;
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = jtag_info->chain_pos;
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fields[2].num_bits = 32;
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fields[2].out_value = instr_buf;
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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jtag_add_runtest(0, -1);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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char* in_string;
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jtag_execute_queue();
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if (in)
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{
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in_string = buf_to_char((u8*)in, 32);
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DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: %s", flip_u32(instr, 32), out, in_string);
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free(in_string);
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}
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else
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DEBUG("instr: 0x%8.8x, out: 0x%8.8x", flip_u32(instr, 32), out);
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}
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#endif
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return ERROR_OK;
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}
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/* just read data (instruction and data-out = don't care) */
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int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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{
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scan_field_t fields[3];
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = NULL;
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fields[0].out_mask = NULL;
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fields[0].in_value = (u8*)in;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 3;
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fields[1].out_value = NULL;
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[2].device = jtag_info->chain_pos;
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fields[2].num_bits = 32;
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fields[2].out_value = NULL;
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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jtag_add_runtest(0, -1);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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char* in_string;
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jtag_execute_queue();
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if (in)
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{
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in_string = buf_to_char((u8*)in, 32);
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DEBUG("in: %s", in_string);
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free(in_string);
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}
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}
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#endif
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return ERROR_OK;
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}
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void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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/* save r0 before using it and put system in ARM state
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* to allow common handling of ARM and THUMB debugging */
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/* fetch STR r0, [r0] */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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/* STR r0, [r0] in Memory */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
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/* MOV r0, r15 fetched, STR in Decode */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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/* nothing fetched, STR r0, [r0] in Memory */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
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/* fetch MOV */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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/* fetch BX */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
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/* NOP fetched, BX in Decode, MOV in Execute */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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/* NOP fetched, BX in Execute (1) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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jtag_execute_queue();
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/* fix program counter:
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* MOV r0, r15 was the 5th instruction (+8)
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* reading PC in Thumb state gives address of instruction + 4
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*/
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*pc -= 0xc;
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}
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void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
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{
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int i;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
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/* fetch NOP, STM in DECODE stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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for (i = 0; i <= 15; i++)
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{
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if (mask & (1 << i))
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/* nothing fetched, STM in MEMORY (i'th cycle) */
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arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
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}
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}
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void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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/* MRS r0, cpsr */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* STR r0, [r15] */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
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/* fetch NOP, STR in DECODE stage */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* fetch NOP, STR in EXECUTE stage (1st cycle) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, STR in MEMORY */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
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}
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void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
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{
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
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/* MSR1 fetched */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
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/* MSR2 fetched, MSR1 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
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/* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
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/* nothing fetched, MSR1 in EXECUTE (2) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, MSR1 in EXECUTE (3) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
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/* nothing fetched, MSR2 in EXECUTE (2) */
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arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
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/* nothing fetched, MSR2 in EXECUTE (3) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* nothing fetched, MSR3 in EXECUTE (2) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* nothing fetched, MSR3 in EXECUTE (3) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* NOP fetched, MSR4 in EXECUTE (1) */
|
|
/* last MSR writes flags, which takes only one cycle */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
}
|
|
|
|
void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
|
|
|
|
/* MSR fetched */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
|
|
/* NOP fetched, MSR in DECODE */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* NOP fetched, MSR in EXECUTE (1) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
/* rot == 4 writes flags, which takes only one cycle */
|
|
if (rot != 4)
|
|
{
|
|
/* nothing fetched, MSR in EXECUTE (2) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* nothing fetched, MSR in EXECUTE (3) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
}
|
|
}
|
|
|
|
void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
|
|
{
|
|
int i;
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* LDMIA r0-15, [r0] at debug speed
|
|
* register values will start to appear on 4th DCLK
|
|
*/
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
|
|
|
|
/* fetch NOP, LDM in DECODE stage */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
for (i = 0; i <= 15; i++)
|
|
{
|
|
if (mask & (1 << i))
|
|
/* nothing fetched, LDM still in EXECUTE (1+i cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
|
|
}
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
void arm9tdmi_load_word_regs(target_t *target, u32 mask)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load-multiple into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_load_hword_reg(target_t *target, int num)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load half-word into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
}
|
|
|
|
void arm9tdmi_load_byte_reg(target_t *target, int num)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load byte into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_store_word_regs(target_t *target, u32 mask)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store-multiple into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_store_hword_reg(target_t *target, int num)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store half-word into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_store_byte_reg(target_t *target, int num)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store byte into the pipeline */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_write_pc(target_t *target, u32 pc)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* LDMIA r0-15, [r0] at debug speed
|
|
* register values will start to appear on 4th DCLK
|
|
*/
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
|
|
|
|
/* fetch NOP, LDM in DECODE stage */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (4th cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
void arm9tdmi_branch_resume(target_t *target)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
|
|
|
|
}
|
|
|
|
void arm9tdmi_branch_resume_thumb(target_t *target)
|
|
{
|
|
DEBUG("");
|
|
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
|
|
|
|
/* LDMIA r0-15, [r0] at debug speed
|
|
* register values will start to appear on 4th DCLK
|
|
*/
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
|
|
|
|
/* fetch NOP, LDM in DECODE stage */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
/* Branch and eXchange */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
|
|
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* fetch NOP, BX in DECODE stage */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* fetch NOP, BX in EXECUTE stage (1st cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
|
|
|
|
/* target is now in Thumb state */
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* clean r0 bits to avoid alignment problems */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
|
|
/* load r0 value, MOV_IM in Decode*/
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR(0, 0), 0, NULL, 0);
|
|
/* fetch NOP, LDR in Decode, MOV_IM in Execute */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
/* fetch NOP, LDR in Execute */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
/* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
|
|
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f6), 0, NULL, 1);
|
|
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
|
|
|
|
}
|
|
|
|
void arm9tdmi_enable_single_step(target_t *target)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm9tdmi_common_t *arm9 = arm7_9->arch_info;
|
|
|
|
if (arm9->has_single_step)
|
|
{
|
|
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
|
|
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
|
|
}
|
|
else
|
|
{
|
|
arm7_9_enable_eice_step(target);
|
|
}
|
|
}
|
|
|
|
void arm9tdmi_disable_single_step(target_t *target)
|
|
{
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm9tdmi_common_t *arm9 = arm7_9->arch_info;
|
|
|
|
if (arm9->has_single_step)
|
|
{
|
|
buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
|
|
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
|
|
}
|
|
else
|
|
{
|
|
arm7_9_disable_eice_step(target);
|
|
}
|
|
}
|
|
|
|
void arm9tdmi_build_reg_cache(target_t *target)
|
|
{
|
|
reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
|
|
/* get pointers to arch-specific information */
|
|
armv4_5_common_t *armv4_5 = target->arch_info;
|
|
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
|
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
|
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
|
|
|
|
|
|
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
|
|
armv4_5->core_cache = (*cache_p);
|
|
|
|
(*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 0);
|
|
arm7_9->eice_cache = (*cache_p)->next;
|
|
|
|
if (arm9tdmi->has_monitor_mode)
|
|
(*cache_p)->next->reg_list[0].size = 6;
|
|
else
|
|
(*cache_p)->next->reg_list[0].size = 4;
|
|
|
|
(*cache_p)->next->reg_list[1].size = 5;
|
|
|
|
}
|
|
|
|
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
|
|
{
|
|
|
|
arm9tdmi_build_reg_cache(target);
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
int arm9tdmi_quit()
|
|
{
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
|
|
{
|
|
armv4_5_common_t *armv4_5;
|
|
arm7_9_common_t *arm7_9;
|
|
|
|
arm7_9 = &arm9tdmi->arm7_9_common;
|
|
armv4_5 = &arm7_9->armv4_5_common;
|
|
|
|
/* prepare JTAG information for the new target */
|
|
arm7_9->jtag_info.chain_pos = chain_pos;
|
|
arm7_9->jtag_info.scann_size = 5;
|
|
|
|
/* register arch-specific functions */
|
|
arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
|
|
arm7_9->change_to_arm = arm9tdmi_change_to_arm;
|
|
arm7_9->read_core_regs = arm9tdmi_read_core_regs;
|
|
arm7_9->read_xpsr = arm9tdmi_read_xpsr;
|
|
|
|
arm7_9->write_xpsr = arm9tdmi_write_xpsr;
|
|
arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
|
|
arm7_9->write_core_regs = arm9tdmi_write_core_regs;
|
|
|
|
arm7_9->load_word_regs = arm9tdmi_load_word_regs;
|
|
arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
|
|
arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
|
|
|
|
arm7_9->store_word_regs = arm9tdmi_store_word_regs;
|
|
arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
|
|
arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
|
|
|
|
arm7_9->write_pc = arm9tdmi_write_pc;
|
|
arm7_9->branch_resume = arm9tdmi_branch_resume;
|
|
arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
|
|
|
|
arm7_9->enable_single_step = arm9tdmi_enable_single_step;
|
|
arm7_9->disable_single_step = arm9tdmi_disable_single_step;
|
|
|
|
arm7_9->pre_debug_entry = NULL;
|
|
arm7_9->post_debug_entry = NULL;
|
|
|
|
arm7_9->pre_restore_context = NULL;
|
|
arm7_9->post_restore_context = NULL;
|
|
|
|
/* initialize arch-specific breakpoint handling */
|
|
buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
|
|
buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
|
|
|
|
arm7_9->sw_bkpts_use_wp = 1;
|
|
arm7_9->sw_bkpts_enabled = 0;
|
|
arm7_9->dbgreq_adjust_pc = 3;
|
|
arm7_9->arch_info = arm9tdmi;
|
|
arm7_9->use_dbgrq = 1;
|
|
|
|
arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
|
|
arm9tdmi->has_monitor_mode = 0;
|
|
arm9tdmi->has_single_step = 0;
|
|
arm9tdmi->arch_info = NULL;
|
|
|
|
if (variant)
|
|
{
|
|
if (strcmp(variant, "arm920t") == 0)
|
|
arm9tdmi->has_single_step = 1;
|
|
else if (strcmp(variant, "arm922t") == 0)
|
|
arm9tdmi->has_single_step = 1;
|
|
else if (strcmp(variant, "arm940t") == 0)
|
|
arm9tdmi->has_single_step = 1;
|
|
}
|
|
|
|
arm7_9_init_arch_info(target, arm7_9);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
|
|
int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
|
|
{
|
|
int chain_pos;
|
|
char *variant = NULL;
|
|
arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
|
|
|
|
if (argc < 4)
|
|
{
|
|
ERROR("'target arm9tdmi' requires at least one additional argument");
|
|
exit(-1);
|
|
}
|
|
|
|
chain_pos = strtoul(args[3], NULL, 0);
|
|
|
|
if (argc >= 5)
|
|
variant = strdup(args[4]);
|
|
|
|
arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
|
|
{
|
|
int retval;
|
|
|
|
retval = arm7_9_register_commands(cmd_ctx);
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|