584 lines
17 KiB
C
584 lines
17 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include "config.h"
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#include "armv4_5.h"
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#include "target.h"
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#include "register.h"
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#include "log.h"
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#include "binarybuffer.h"
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#include "command.h"
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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bitfield_desc_t armv4_5_psr_bitfield_desc[] =
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{
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{"M[4:0]", 5},
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{"T", 1},
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{"F", 1},
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{"I", 1},
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{"reserved", 16},
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{"J", 1},
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{"reserved", 2},
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{"Q", 1},
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{"V", 1},
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{"C", 1},
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{"Z", 1},
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{"N", 1},
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};
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char* armv4_5_core_reg_list[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
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"r13_irq", "lr_irq",
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"r13_svc", "lr_svc",
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"r13_abt", "lr_abt",
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"r13_und", "lr_und",
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"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
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};
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char* armv4_5_mode_strings[] =
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{
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"User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
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};
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char* armv4_5_state_strings[] =
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{
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"ARM", "Thumb", "Jazelle"
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};
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int armv4_5_core_reg_arch_type = -1;
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armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
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{
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{0, ARMV4_5_MODE_ANY, NULL, NULL},
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{1, ARMV4_5_MODE_ANY, NULL, NULL},
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{2, ARMV4_5_MODE_ANY, NULL, NULL},
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{3, ARMV4_5_MODE_ANY, NULL, NULL},
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{4, ARMV4_5_MODE_ANY, NULL, NULL},
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{5, ARMV4_5_MODE_ANY, NULL, NULL},
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{6, ARMV4_5_MODE_ANY, NULL, NULL},
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{7, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_ANY, NULL, NULL},
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{9, ARMV4_5_MODE_ANY, NULL, NULL},
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{10, ARMV4_5_MODE_ANY, NULL, NULL},
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{11, ARMV4_5_MODE_ANY, NULL, NULL},
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{12, ARMV4_5_MODE_ANY, NULL, NULL},
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{13, ARMV4_5_MODE_USR, NULL, NULL},
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{14, ARMV4_5_MODE_USR, NULL, NULL},
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{15, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_FIQ, NULL, NULL},
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{9, ARMV4_5_MODE_FIQ, NULL, NULL},
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{10, ARMV4_5_MODE_FIQ, NULL, NULL},
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{11, ARMV4_5_MODE_FIQ, NULL, NULL},
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{12, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_FIQ, NULL, NULL},
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{14, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_IRQ, NULL, NULL},
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{14, ARMV4_5_MODE_IRQ, NULL, NULL},
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{13, ARMV4_5_MODE_SVC, NULL, NULL},
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{14, ARMV4_5_MODE_SVC, NULL, NULL},
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{13, ARMV4_5_MODE_ABT, NULL, NULL},
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{14, ARMV4_5_MODE_ABT, NULL, NULL},
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{13, ARMV4_5_MODE_UND, NULL, NULL},
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{14, ARMV4_5_MODE_UND, NULL, NULL},
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{16, ARMV4_5_MODE_ANY, NULL, NULL},
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{16, ARMV4_5_MODE_FIQ, NULL, NULL},
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{16, ARMV4_5_MODE_IRQ, NULL, NULL},
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{16, ARMV4_5_MODE_SVC, NULL, NULL},
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{16, ARMV4_5_MODE_ABT, NULL, NULL},
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{16, ARMV4_5_MODE_UND, NULL, NULL}
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};
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/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
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int armv4_5_core_reg_map[7][17] =
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{
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{ /* USR */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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},
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{ /* FIQ */
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0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
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},
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{ /* IRQ */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
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},
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{ /* SVC */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
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},
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{ /* ABT */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
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},
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{ /* UND */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
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},
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{ /* SYS */
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
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}
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};
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u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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reg_t armv4_5_gdb_dummy_fp_reg =
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{
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"GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
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};
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u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
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reg_t armv4_5_gdb_dummy_fps_reg =
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{
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"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
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};
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/* map psr mode bits to linear number */
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int armv4_5_mode_to_number(enum armv4_5_mode mode)
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{
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switch (mode)
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{
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case 16: return 0; break;
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case 17: return 1; break;
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case 18: return 2; break;
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case 19: return 3; break;
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case 23: return 4; break;
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case 27: return 5; break;
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case 31: return 6; break;
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case -1: return 0; break; /* map MODE_ANY to user mode */
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default:
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ERROR("invalid mode value encountered");
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return -1;
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}
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}
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/* map linear number to mode bits */
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enum armv4_5_mode armv4_5_number_to_mode(int number)
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{
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switch(number)
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{
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case 0: return ARMV4_5_MODE_USR; break;
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case 1: return ARMV4_5_MODE_FIQ; break;
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case 2: return ARMV4_5_MODE_IRQ; break;
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case 3: return ARMV4_5_MODE_SVC; break;
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case 4: return ARMV4_5_MODE_ABT; break;
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case 5: return ARMV4_5_MODE_UND; break;
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case 6: return ARMV4_5_MODE_SYS; break;
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default:
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ERROR("mode index out of bounds");
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return -1;
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}
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};
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int armv4_5_get_core_reg(reg_t *reg)
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{
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int retval;
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armv4_5_core_reg_t *armv4_5 = reg->arch_info;
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target_t *target = armv4_5->target;
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if (target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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//retval = armv4_5->armv4_5_common->full_context(target);
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retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
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return retval;
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}
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int armv4_5_set_core_reg(reg_t *reg, u32 value)
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{
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armv4_5_core_reg_t *armv4_5 = reg->arch_info;
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target_t *target = armv4_5->target;
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if (target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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buf_set_u32(reg->value, 0, 32, value);
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reg->dirty = 1;
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reg->valid = 1;
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return ERROR_OK;
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}
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int armv4_5_invalidate_core_regs(target_t *target)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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int i;
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for (i = 0; i < 37; i++)
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{
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armv4_5->core_cache->reg_list[i].valid = 0;
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armv4_5->core_cache->reg_list[i].dirty = 0;
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}
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return ERROR_OK;
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}
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reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
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{
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int num_regs = 37;
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reg_cache_t *cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
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armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs);
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int i;
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cache->name = "arm v4/5 registers";
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cache->next = NULL;
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cache->reg_list = reg_list;
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cache->num_regs = num_regs;
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if (armv4_5_core_reg_arch_type == -1)
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armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
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for (i = 0; i < 37; i++)
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{
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arch_info[i] = armv4_5_core_reg_list_arch_info[i];
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arch_info[i].target = target;
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arch_info[i].armv4_5_common = armv4_5_common;
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reg_list[i].name = armv4_5_core_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].bitfield_desc = NULL;
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reg_list[i].num_bitfields = 0;
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reg_list[i].arch_type = armv4_5_core_reg_arch_type;
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reg_list[i].arch_info = &arch_info[i];
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}
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return cache;
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}
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int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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ERROR("BUG: called for a non-ARMv4/5 target");
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exit(-1);
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}
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snprintf(buf, buf_size,
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"target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
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armv4_5_state_strings[armv4_5->core_state],
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target_debug_reason_strings[target->debug_reason],
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armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
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return ERROR_OK;
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}
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int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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char output[128];
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int output_len;
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int mode, num;
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
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return ERROR_OK;
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}
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if (target->state != TARGET_HALTED)
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{
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command_print(cmd_ctx, "error: target must be halted for register accesses");
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return ERROR_OK;
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}
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for (num = 0; num <= 15; num++)
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{
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output_len = 0;
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for (mode = 0; mode < 6; mode++)
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{
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if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
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{
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armv4_5->full_context(target);
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}
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output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
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buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
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}
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command_print(cmd_ctx, output);
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}
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command_print(cmd_ctx, " cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
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buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
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return ERROR_OK;
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}
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int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv4_5_common_t *armv4_5 = target->arch_info;
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if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
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{
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command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
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return ERROR_OK;
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}
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if (argc > 0)
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{
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if (strcmp(args[0], "arm") == 0)
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{
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armv4_5->core_state = ARMV4_5_STATE_ARM;
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}
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if (strcmp(args[0], "thumb") == 0)
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{
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armv4_5->core_state = ARMV4_5_STATE_THUMB;
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}
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}
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command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
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return ERROR_OK;
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}
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int armv4_5_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *armv4_5_cmd;
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armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, NULL);
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register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
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register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
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return ERROR_OK;
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}
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int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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int i;
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if (target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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*reg_list_size = 26;
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*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
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for (i = 0; i < 16; i++)
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{
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(*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
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}
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for (i = 16; i < 24; i++)
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{
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(*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
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}
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(*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
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(*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
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return ERROR_OK;
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}
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int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
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{
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armv4_5_common_t *armv4_5 = target->arch_info;
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armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
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enum armv4_5_state core_state = armv4_5->core_state;
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enum armv4_5_mode core_mode = armv4_5->core_mode;
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u32 context[17];
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u32 cpsr;
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int exit_breakpoint_size = 0;
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int i;
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int retval = ERROR_OK;
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|
|
if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
|
|
{
|
|
ERROR("current target isn't an ARMV4/5 target");
|
|
return ERROR_TARGET_INVALID;
|
|
}
|
|
|
|
if (target->state != TARGET_HALTED)
|
|
{
|
|
WARNING("target not halted");
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
}
|
|
|
|
for (i = 0; i <= 16; i++)
|
|
{
|
|
if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
|
|
armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
|
|
context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
|
|
}
|
|
cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
|
|
|
|
for (i = 0; i < num_mem_params; i++)
|
|
{
|
|
target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
|
|
}
|
|
|
|
for (i = 0; i < num_reg_params; i++)
|
|
{
|
|
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
|
|
if (!reg)
|
|
{
|
|
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
|
|
exit(-1);
|
|
}
|
|
|
|
if (reg->size != reg_params[i].size)
|
|
{
|
|
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
|
|
exit(-1);
|
|
}
|
|
|
|
armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32));
|
|
}
|
|
|
|
armv4_5->core_state = armv4_5_algorithm_info->core_state;
|
|
if (armv4_5->core_state == ARMV4_5_STATE_ARM)
|
|
exit_breakpoint_size = 4;
|
|
else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
|
|
exit_breakpoint_size = 2;
|
|
else
|
|
{
|
|
ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
|
|
exit(-1);
|
|
}
|
|
|
|
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
|
|
{
|
|
DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
|
|
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
|
|
}
|
|
|
|
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
|
|
{
|
|
ERROR("can't add breakpoint to finish algorithm execution");
|
|
return ERROR_TARGET_FAILURE;
|
|
}
|
|
|
|
target->type->resume(target, 0, entry_point, 1, 1);
|
|
target->type->poll(target);
|
|
|
|
while (target->state != TARGET_HALTED)
|
|
{
|
|
usleep(10000);
|
|
target->type->poll(target);
|
|
if ((timeout_ms -= 10) <= 0)
|
|
{
|
|
ERROR("timeout waiting for algorithm to complete, trying to halt target");
|
|
target->type->halt(target);
|
|
timeout_ms = 1000;
|
|
while (target->state != TARGET_HALTED)
|
|
{
|
|
usleep(10000);
|
|
target->type->poll(target);
|
|
if ((timeout_ms -= 10) <= 0)
|
|
{
|
|
ERROR("target didn't reenter debug state, exiting");
|
|
exit(-1);
|
|
}
|
|
}
|
|
retval = ERROR_TARGET_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
breakpoint_remove(target, exit_point);
|
|
|
|
for (i = 0; i < num_mem_params; i++)
|
|
{
|
|
if (mem_params[i].direction != PARAM_OUT)
|
|
target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
|
|
}
|
|
|
|
for (i = 0; i < num_reg_params; i++)
|
|
{
|
|
if (reg_params[i].direction != PARAM_OUT)
|
|
{
|
|
|
|
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
|
|
if (!reg)
|
|
{
|
|
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
|
|
exit(-1);
|
|
}
|
|
|
|
if (reg->size != reg_params[i].size)
|
|
{
|
|
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
|
|
exit(-1);
|
|
}
|
|
|
|
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
|
|
}
|
|
}
|
|
|
|
for (i = 0; i <= 16; i++)
|
|
{
|
|
DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32));
|
|
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
|
|
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
|
|
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
|
|
}
|
|
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
|
|
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
|
|
|
|
armv4_5->core_state = core_state;
|
|
armv4_5->core_mode = core_mode;
|
|
|
|
return retval;
|
|
}
|
|
|
|
int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
|
|
{
|
|
target->arch_info = armv4_5;
|
|
|
|
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
|
|
armv4_5->core_state = ARMV4_5_STATE_ARM;
|
|
armv4_5->core_mode = ARMV4_5_MODE_USR;
|
|
|
|
return ERROR_OK;
|
|
}
|