359 lines
9.9 KiB
C
359 lines
9.9 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include "arm7_9_common.h"
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#include "log.h"
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#include "command.h"
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#include "armv4_5_mmu.h"
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#include <stdlib.h>
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u32 armv4mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap);
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int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
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int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer);
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char* armv4_5_mmu_page_type_names[] =
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{
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"section", "large page", "small page", "tiny page"
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};
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u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 va, int *type, u32 *cb, int *domain, u32 *ap)
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{
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u32 first_lvl_descriptor = 0x0;
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u32 second_lvl_descriptor = 0x0;
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u32 ttb = armv4_5_mmu->get_ttb(target);
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armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
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4, 1, (u8*)&first_lvl_descriptor);
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DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
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if ((first_lvl_descriptor & 0x3) == 0)
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{
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*type = -1;
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
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{
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*type = -1;
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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/* domain is always specified in bits 8-5 */
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*domain = (first_lvl_descriptor & 0x1e0) >> 5;
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if ((first_lvl_descriptor & 0x3) == 2)
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{
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/* section descriptor */
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*type = ARMV4_5_SECTION;
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*cb = (first_lvl_descriptor & 0xc) >> 2;
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*ap = (first_lvl_descriptor & 0xc00) >> 10;
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return (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
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}
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if ((first_lvl_descriptor & 0x3) == 1)
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{
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/* coarse page table */
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armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
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4, 1, (u8*)&second_lvl_descriptor);
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}
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if ((first_lvl_descriptor & 0x3) == 3)
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{
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/* fine page table */
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armv4_5_mmu_read_physical(target, armv4_5_mmu,
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(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
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4, 1, (u8*)&second_lvl_descriptor);
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}
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DEBUG("2nd lvl desc: %8.8x", first_lvl_descriptor);
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if ((second_lvl_descriptor & 0x3) == 0)
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{
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*type = -1;
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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/* cacheable/bufferable is always specified in bits 3-2 */
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*cb = (second_lvl_descriptor & 0xc) >> 2;
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if ((second_lvl_descriptor & 0x3) == 1)
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{
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/* large page descriptor */
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*type = ARMV4_5_LARGE_PAGE;
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*ap = (second_lvl_descriptor & 0xff0) >> 4;
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return (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
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}
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if ((second_lvl_descriptor & 0x3) == 2)
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{
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/* small page descriptor */
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*type = ARMV4_5_SMALL_PAGE;
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*ap = (second_lvl_descriptor & 0xff0) >> 4;
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return (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
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}
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if ((second_lvl_descriptor & 0x3) == 3)
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{
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/* tiny page descriptor */
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*type = ARMV4_5_TINY_PAGE;
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*ap = (second_lvl_descriptor & 0x30) >> 4;
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return (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
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}
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/* should not happen */
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*type = -1;
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return ERROR_TARGET_TRANSLATION_FAULT;
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}
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int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer)
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{
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int retval;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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/* disable MMU and data (or unified) cache */
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armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
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retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
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/* reenable MMU / cache */
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armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
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armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
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armv4_5_mmu->armv4_5_cache.i_cache_enabled);
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return retval;
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}
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int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, u32 address, u32 size, u32 count, u8 *buffer)
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{
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int retval;
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if (target->state != TARGET_HALTED)
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return ERROR_TARGET_NOT_HALTED;
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/* disable MMU and data (or unified) cache */
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armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
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retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
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/* reenable MMU / cache */
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armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
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armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
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armv4_5_mmu->armv4_5_cache.i_cache_enabled);
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return retval;
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}
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int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
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{
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u32 va;
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u32 pa;
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int type;
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u32 cb;
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int domain;
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u32 ap;
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if (target->state != TARGET_HALTED)
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{
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command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command");
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return ERROR_OK;
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}
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if (argc == 0)
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{
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command_print(cmd_ctx, "usage: virt2phys <virtual address>");
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return ERROR_OK;
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}
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if (argc == 1)
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{
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va = strtoul(args[0], NULL, 0);
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pa = armv4_5_mmu_translate_va(target, armv4_5_mmu, va, &type, &cb, &domain, &ap);
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if (type == -1)
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{
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switch (pa)
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{
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case ERROR_TARGET_TRANSLATION_FAULT:
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command_print(cmd_ctx, "no valid translation for 0x%8.8x", va);
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break;
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default:
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command_print(cmd_ctx, "unknown translation error");
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}
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return ERROR_OK;
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}
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command_print(cmd_ctx, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
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va, pa, armv4_5_mmu_page_type_names[type], cb, domain, ap);
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}
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return ERROR_OK;
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}
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int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
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{
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int count = 1;
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int size = 4;
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u32 address = 0;
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int i;
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char output[128];
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int output_len;
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int retval;
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u8 *buffer;
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if (target->state != TARGET_HALTED)
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{
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command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
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return ERROR_OK;
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}
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if (argc < 1)
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return ERROR_OK;
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if (argc == 2)
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count = strtoul(args[1], NULL, 0);
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address = strtoul(args[0], NULL, 0);
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switch (cmd[2])
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{
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case 'w':
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size = 4;
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break;
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case 'h':
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size = 2;
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break;
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case 'b':
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size = 1;
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break;
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default:
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return ERROR_OK;
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}
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buffer = calloc(count, size);
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if ((retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK)
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{
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switch (retval)
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{
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case ERROR_TARGET_UNALIGNED_ACCESS:
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command_print(cmd_ctx, "error: address not aligned");
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break;
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case ERROR_TARGET_NOT_HALTED:
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command_print(cmd_ctx, "error: target must be halted for memory accesses");
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break;
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case ERROR_TARGET_DATA_ABORT:
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command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
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break;
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default:
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command_print(cmd_ctx, "error: unknown error");
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}
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}
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output_len = 0;
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for (i = 0; i < count; i++)
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{
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if (i%8 == 0)
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output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size));
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switch (size)
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{
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case 4:
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output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", ((u32*)buffer)[i]);
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break;
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case 2:
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output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", ((u16*)buffer)[i]);
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break;
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case 1:
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output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", ((u8*)buffer)[i]);
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break;
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}
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if ((i%8 == 7) || (i == count - 1))
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{
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command_print(cmd_ctx, output);
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output_len = 0;
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}
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}
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free(buffer);
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return ERROR_OK;
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}
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int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
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{
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u32 address = 0;
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u32 value = 0;
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int retval;
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if (target->state != TARGET_HALTED)
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{
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command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
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return ERROR_OK;
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}
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if (argc < 2)
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return ERROR_OK;
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address = strtoul(args[0], NULL, 0);
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value = strtoul(args[1], NULL, 0);
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switch (cmd[2])
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{
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case 'w':
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retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, (u8*)&value);
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break;
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case 'h':
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retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, (u8*)&value);
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break;
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case 'b':
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retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, (u8*)&value);
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break;
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default:
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return ERROR_OK;
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}
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switch (retval)
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{
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case ERROR_TARGET_UNALIGNED_ACCESS:
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command_print(cmd_ctx, "error: address not aligned");
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break;
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case ERROR_TARGET_DATA_ABORT:
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command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
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break;
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case ERROR_TARGET_NOT_HALTED:
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command_print(cmd_ctx, "error: target must be halted for memory accesses");
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break;
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case ERROR_OK:
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break;
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default:
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command_print(cmd_ctx, "error: unknown error");
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}
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return ERROR_OK;
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}
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