410 lines
12 KiB
C
410 lines
12 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#include "config.h"
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#include "etm.h"
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#include "armv4_5.h"
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#include "arm7_9_common.h"
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#include "log.h"
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#include "arm_jtag.h"
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#include "types.h"
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#include "binarybuffer.h"
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#include "target.h"
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#include "register.h"
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#include "jtag.h"
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#include <stdlib.h>
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bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
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{
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{"R", 1},
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{"W", 1},
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{"reserved", 26},
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{"version", 4}
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};
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int etm_reg_arch_info[] =
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{
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
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0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
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0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
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0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
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0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
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0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
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0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
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0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
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0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
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0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
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0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
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0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
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};
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int etm_reg_arch_size_info[] =
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{
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32, 32, 17, 8, 3, 9, 32, 17,
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26, 16, 25, 8, 17, 32, 32, 17,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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32, 32, 32, 32, 32, 32, 32, 32,
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16, 16, 16, 16, 18, 18, 18, 18,
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17, 17, 17, 17, 16, 16, 16, 16,
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17, 17, 17, 17, 17, 17, 2,
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17, 17, 17, 17, 32, 32, 32, 32
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};
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char* etm_reg_list[] =
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{
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"ETM_CTRL",
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"ETM_CONFIG",
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"ETM_TRIG_EVENT",
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"ETM_MMD_CTRL",
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"ETM_STATUS",
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"ETM_SYS_CONFIG",
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"ETM_TRACE_RESOURCE_CTRL",
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"ETM_TRACE_EN_CTRL2",
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"ETM_TRACE_EN_EVENT",
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"ETM_TRACE_EN_CTRL1",
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"ETM_FIFOFULL_REGION",
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"ETM_FIFOFULL_LEVEL",
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"ETM_VIEWDATA_EVENT",
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"ETM_VIEWDATA_CTRL1",
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"ETM_VIEWDATA_CTRL2",
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"ETM_VIEWDATA_CTRL3",
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"ETM_ADDR_COMPARATOR_VALUE1",
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"ETM_ADDR_COMPARATOR_VALUE2",
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"ETM_ADDR_COMPARATOR_VALUE3",
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"ETM_ADDR_COMPARATOR_VALUE4",
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"ETM_ADDR_COMPARATOR_VALUE5",
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"ETM_ADDR_COMPARATOR_VALUE6",
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"ETM_ADDR_COMPARATOR_VALUE7",
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"ETM_ADDR_COMPARATOR_VALUE8",
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"ETM_ADDR_COMPARATOR_VALUE9",
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"ETM_ADDR_COMPARATOR_VALUE10",
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"ETM_ADDR_COMPARATOR_VALUE11",
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"ETM_ADDR_COMPARATOR_VALUE12",
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"ETM_ADDR_COMPARATOR_VALUE13",
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"ETM_ADDR_COMPARATOR_VALUE14",
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"ETM_ADDR_COMPARATOR_VALUE15",
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"ETM_ADDR_COMPARATOR_VALUE16",
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"ETM_ADDR_ACCESS_TYPE1",
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"ETM_ADDR_ACCESS_TYPE2",
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"ETM_ADDR_ACCESS_TYPE3",
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"ETM_ADDR_ACCESS_TYPE4",
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"ETM_ADDR_ACCESS_TYPE5",
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"ETM_ADDR_ACCESS_TYPE6",
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"ETM_ADDR_ACCESS_TYPE7",
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"ETM_ADDR_ACCESS_TYPE8",
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"ETM_ADDR_ACCESS_TYPE9",
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"ETM_ADDR_ACCESS_TYPE10",
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"ETM_ADDR_ACCESS_TYPE11",
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"ETM_ADDR_ACCESS_TYPE12",
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"ETM_ADDR_ACCESS_TYPE13",
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"ETM_ADDR_ACCESS_TYPE14",
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"ETM_ADDR_ACCESS_TYPE15",
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"ETM_ADDR_ACCESS_TYPE16",
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"ETM_DATA_COMPARATOR_VALUE1",
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"ETM_DATA_COMPARATOR_VALUE2",
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"ETM_DATA_COMPARATOR_VALUE3",
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"ETM_DATA_COMPARATOR_VALUE4",
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"ETM_DATA_COMPARATOR_VALUE5",
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"ETM_DATA_COMPARATOR_VALUE6",
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"ETM_DATA_COMPARATOR_VALUE7",
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"ETM_DATA_COMPARATOR_VALUE8",
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"ETM_DATA_COMPARATOR_VALUE9",
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"ETM_DATA_COMPARATOR_VALUE10",
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"ETM_DATA_COMPARATOR_VALUE11",
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"ETM_DATA_COMPARATOR_VALUE12",
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"ETM_DATA_COMPARATOR_VALUE13",
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"ETM_DATA_COMPARATOR_VALUE14",
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"ETM_DATA_COMPARATOR_VALUE15",
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"ETM_DATA_COMPARATOR_VALUE16",
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"ETM_DATA_COMPARATOR_MASK1",
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"ETM_DATA_COMPARATOR_MASK2",
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"ETM_DATA_COMPARATOR_MASK3",
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"ETM_DATA_COMPARATOR_MASK4",
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"ETM_DATA_COMPARATOR_MASK5",
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"ETM_DATA_COMPARATOR_MASK6",
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"ETM_DATA_COMPARATOR_MASK7",
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"ETM_DATA_COMPARATOR_MASK8",
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"ETM_DATA_COMPARATOR_MASK9",
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"ETM_DATA_COMPARATOR_MASK10",
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"ETM_DATA_COMPARATOR_MASK11",
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"ETM_DATA_COMPARATOR_MASK12",
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"ETM_DATA_COMPARATOR_MASK13",
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"ETM_DATA_COMPARATOR_MASK14",
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"ETM_DATA_COMPARATOR_MASK15",
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"ETM_DATA_COMPARATOR_MASK16",
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"ETM_COUNTER_INITAL_VALUE1",
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"ETM_COUNTER_INITAL_VALUE2",
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"ETM_COUNTER_INITAL_VALUE3",
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"ETM_COUNTER_INITAL_VALUE4",
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"ETM_COUNTER_ENABLE1",
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"ETM_COUNTER_ENABLE2",
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"ETM_COUNTER_ENABLE3",
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"ETM_COUNTER_ENABLE4",
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"ETM_COUNTER_RELOAD_VALUE1",
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"ETM_COUNTER_RELOAD_VALUE2",
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"ETM_COUNTER_RELOAD_VALUE3",
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"ETM_COUNTER_RELOAD_VALUE4",
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"ETM_COUNTER_VALUE1",
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"ETM_COUNTER_VALUE2",
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"ETM_COUNTER_VALUE3",
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"ETM_COUNTER_VALUE4",
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"ETM_SEQUENCER_CTRL1",
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"ETM_SEQUENCER_CTRL2",
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"ETM_SEQUENCER_CTRL3",
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"ETM_SEQUENCER_CTRL4",
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"ETM_SEQUENCER_CTRL5",
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"ETM_SEQUENCER_CTRL6",
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"ETM_SEQUENCER_STATE",
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"ETM_EXTERNAL_OUTPUT1",
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"ETM_EXTERNAL_OUTPUT2",
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"ETM_EXTERNAL_OUTPUT3",
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"ETM_EXTERNAL_OUTPUT4",
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"ETM_CONTEXTID_COMPARATOR_VALUE1",
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"ETM_CONTEXTID_COMPARATOR_VALUE2",
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"ETM_CONTEXTID_COMPARATOR_VALUE3",
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"ETM_CONTEXTID_COMPARATOR_MASK"
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};
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int etm_reg_arch_type = -1;
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int etm_get_reg(reg_t *reg);
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int etm_set_reg(reg_t *reg, u32 value);
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int etm_write_reg(reg_t *reg, u32 value);
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int etm_read_reg(reg_t *reg);
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reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg)
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{
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reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = NULL;
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etm_reg_t *arch_info = NULL;
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int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
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int i;
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/* register a register arch-type for etm registers only once */
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if (etm_reg_arch_type == -1)
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etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
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/* the actual registers are kept in two arrays */
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reg_list = calloc(num_regs, sizeof(reg_t));
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arch_info = calloc(num_regs, sizeof(etm_reg_t));
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/* fill in values for the reg cache */
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reg_cache->name = "etm registers";
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reg_cache->next = NULL;
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reg_cache->reg_list = reg_list;
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reg_cache->num_regs = num_regs;
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/* set up registers */
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for (i = 0; i < num_regs; i++)
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{
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reg_list[i].name = etm_reg_list[i];
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reg_list[i].size = 32;
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].bitfield_desc = NULL;
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reg_list[i].num_bitfields = 0;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].arch_type = etm_reg_arch_type;
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reg_list[i].size = etm_reg_arch_size_info[i];
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arch_info[i].addr = etm_reg_arch_info[i];
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arch_info[i].jtag_info = jtag_info;
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}
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return reg_cache;
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}
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int etm_get_reg(reg_t *reg)
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{
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if (etm_read_reg(reg) != ERROR_OK)
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{
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ERROR("BUG: error scheduling etm register read");
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exit(-1);
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}
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if (jtag_execute_queue() != ERROR_OK)
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{
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ERROR("register read failed");
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}
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return ERROR_OK;
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}
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int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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{
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etm_reg_t *etm_reg = reg->arch_info;
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u8 reg_addr = etm_reg->addr & 0x7f;
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scan_field_t fields[3];
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DEBUG("%i", etm_reg->addr);
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(etm_reg->jtag_info, 0x6);
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arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr);
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fields[0].device = etm_reg->jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = reg->value;
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fields[0].out_mask = NULL;
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fields[0].in_value = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = etm_reg->jtag_info->chain_pos;
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fields[1].num_bits = 7;
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fields[1].out_value = malloc(1);
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = etm_reg->jtag_info->chain_pos;
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fields[2].num_bits = 1;
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fields[2].out_value = malloc(1);
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buf_set_u32(fields[2].out_value, 0, 1, 0);
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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fields[0].in_value = reg->value;
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fields[0].in_check_value = check_value;
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fields[0].in_check_mask = check_mask;
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jtag_add_dr_scan(3, fields, -1);
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free(fields[1].out_value);
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free(fields[2].out_value);
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return ERROR_OK;
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}
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int etm_read_reg(reg_t *reg)
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{
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return etm_read_reg_w_check(reg, NULL, NULL);
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}
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int etm_set_reg(reg_t *reg, u32 value)
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{
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if (etm_write_reg(reg, value) != ERROR_OK)
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{
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ERROR("BUG: error scheduling etm register write");
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exit(-1);
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}
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buf_set_u32(reg->value, 0, reg->size, value);
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reg->valid = 1;
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reg->dirty = 0;
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return ERROR_OK;
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}
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int etm_set_reg_w_exec(reg_t *reg, u32 value)
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{
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etm_set_reg(reg, value);
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if (jtag_execute_queue() != ERROR_OK)
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{
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ERROR("register write failed");
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exit(-1);
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}
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return ERROR_OK;
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}
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int etm_write_reg(reg_t *reg, u32 value)
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{
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etm_reg_t *etm_reg = reg->arch_info;
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u8 reg_addr = etm_reg->addr & 0x7f;
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scan_field_t fields[3];
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DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(etm_reg->jtag_info, 0x6);
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arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr);
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fields[0].device = etm_reg->jtag_info->chain_pos;
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fields[0].num_bits = 32;
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fields[0].out_value = malloc(4);
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buf_set_u32(fields[0].out_value, 0, 32, value);
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fields[0].out_mask = NULL;
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fields[0].in_value = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = etm_reg->jtag_info->chain_pos;
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fields[1].num_bits = 7;
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fields[1].out_value = malloc(1);
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buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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fields[2].device = etm_reg->jtag_info->chain_pos;
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fields[2].num_bits = 1;
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fields[2].out_value = malloc(1);
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buf_set_u32(fields[2].out_value, 0, 1, 1);
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fields[2].out_mask = NULL;
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fields[2].in_value = NULL;
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fields[2].in_check_value = NULL;
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fields[2].in_check_mask = NULL;
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fields[2].in_handler = NULL;
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fields[2].in_handler_priv = NULL;
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jtag_add_dr_scan(3, fields, -1);
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free(fields[0].out_value);
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free(fields[1].out_value);
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free(fields[2].out_value);
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return ERROR_OK;
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}
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int etm_store_reg(reg_t *reg)
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{
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return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
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}
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