8b7f813b23
Tweak the csb337 code so that it doesn't enable alignment traps when it completes the "reset init" sequence. It turns out that the current CFI code reliably triggers such traps. git-svn-id: svn://svn.berlios.de/openocd/trunk@2179 b42882b7-edfa-0310-969c-e2dbd0fdcd60
117 lines
2.8 KiB
INI
117 lines
2.8 KiB
INI
# Cogent CSB337
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# http://cogcomp.com/csb_csb337.htm
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source [find target/at91rm9200.cfg]
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# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
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flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
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# ETM9 trace port connector present on this board, 16 data pins.
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if { [info exists ETM_DRIVER] } {
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etm config $_TARGETNAME 16 normal half $ETM_DRIVER
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# OpenOCD may someday support a real trace port driver...
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# system config file would need to configure it.
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} else {
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etm config $_TARGETNAME 16 normal half dummy
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etm_dummy config $_TARGETNAME
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}
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proc csb337_clk_init { } {
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# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
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jtag_khz 8
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# CKGR_MOR: start main oscillator (3.6864 MHz)
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mww 0xfffffc20 0xff01
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sleep 10
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# CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
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mww 0xfffffc28 0x20313e01
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# CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
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mww 0xfffffc2c 0x12703e18
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# let PLLs lock
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sleep 10
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# PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
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mww 0xfffffc30 0x0302
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sleep 20
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# CPU is in Normal Mode ... allows faster JTAG clock speed
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jtag_khz 40000
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}
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proc csb337_nor_init { } {
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# SMC_CSR0: adjust timings (10 wait states)
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mww 0xffffff70 0x1100318a
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flash probe 0
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}
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proc csb337_sdram_init { } {
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# enable PIOC clock
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mww 0xfffffc10 0x0010
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# PC31..PC16 are D31..D16, with internal pullups like D15..D0
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mww 0xfffff870 0xffff0000
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mww 0xfffff874 0x0
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mww 0xfffff804 0xffff0000
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# SDRC_CR: set timings
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mww 0xffffff98 0x2188b0d5
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# SDRC_MR: issue all banks precharge to SDRAM
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mww 0xffffff90 2
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mww 0x20000000 0
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# SDRC_MR: 8 autorefresh cycles
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mww 0xffffff90 4
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
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mww 0xffffff90 3
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mww 0x20000080 0
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# SDRC_TR: set refresh rate
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mww 0xffffff94 0x200
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mww 0x20000000 0
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# SDRC_MR: normal mode, 32 bit bus
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mww 0xffffff90 0
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mww 0x20000000 0
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}
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# The rm9200 chip has just been reset. Bring it up far enough
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# that we can write flash or run code from SDRAM.
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proc csb337_reset_init { } {
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csb337_clk_init
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# EBI_CSA: CS0 = NOR, CS1 = SDRAM
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mww 0xffffff60 0x02
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csb337_nor_init
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csb337_sdram_init
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# Update CP15 control register ... we don't seem to be able to
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# read/modify/write its value through a TCL variable, so just
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# write it. Fields are zero unless listed here ... and note
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# that OpenOCD numbers this register "2", not "1" (!).
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#
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# - Core to use Async Clocking mode (so it uses 184 MHz most
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# of the time instead of limiting to the master clock rate):
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# iA(31) = 1, nF(30) = 1
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# - Icache on (it's disabled now, slowing i-fetches)
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# I(12) = 1
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# - Reserved/ones
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# 6:3 = 1
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arm920t cp15 2 0xc0001078
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}
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$_TARGETNAME configure -event reset-init {csb337_reset_init}
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# vim:syntax tcl
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