156 lines
8.1 KiB
C
156 lines
8.1 KiB
C
/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by Hongtao Zheng *
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* hontor@126.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARM7_9_COMMON_H
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#define ARM7_9_COMMON_H
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#include "breakpoints.h"
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#include "etm.h"
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#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
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/**
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* Structure for items that are common between both ARM7 and ARM9 targets.
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*/
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typedef struct arm7_9_common_s
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{
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uint32_t common_magic;
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arm_jtag_t jtag_info; /**< JTAG information for target */
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reg_cache_t *eice_cache; /**< Embedded ICE register cache */
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uint32_t arm_bkpt; /**< ARM breakpoint instruction */
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uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
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int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
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int breakpoint_count; /**< Current number of set breakpoints */
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int wp_available; /**< Current number of available watchpoint units */
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int wp_available_max; /**< Maximum number of available watchpoint units */
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int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
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int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
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int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
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int force_hw_bkpts;
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int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
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int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
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int need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
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etm_context_t *etm_ctx;
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int has_single_step;
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int has_monitor_mode;
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int has_vector_catch; /**< Specifies if the target has a reset vector catch */
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int debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
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struct working_area_s *dcc_working_area;
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int fast_memory_access;
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int dcc_downloads;
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int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
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void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
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void (*read_core_regs)(target_t *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
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void (*read_core_regs_target_buffer)(target_t *target, uint32_t mask, void *buffer, int size);
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void (*read_xpsr)(target_t *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
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void (*write_xpsr)(target_t *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
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void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
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void (*write_core_regs)(target_t *target, uint32_t mask, uint32_t core_regs[16]);
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void (*load_word_regs)(target_t *target, uint32_t mask);
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void (*load_hword_reg)(target_t *target, int num);
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void (*load_byte_reg)(target_t *target, int num);
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void (*store_word_regs)(target_t *target, uint32_t mask);
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void (*store_hword_reg)(target_t *target, int num);
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void (*store_byte_reg)(target_t *target, int num);
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void (*write_pc)(target_t *target, uint32_t pc); /**< Function for writing to the program counter */
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void (*branch_resume)(target_t *target);
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void (*branch_resume_thumb)(target_t *target);
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void (*enable_single_step)(target_t *target, uint32_t next_pc);
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void (*disable_single_step)(target_t *target);
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void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
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void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */
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void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
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void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
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void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
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armv4_5_common_t armv4_5_common;
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void *arch_info;
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} arm7_9_common_t;
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int arm7_9_register_commands(struct command_context_s *cmd_ctx);
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int arm7_9_poll(target_t *target);
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int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer);
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int arm7_9_setup(target_t *target);
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int arm7_9_assert_reset(target_t *target);
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int arm7_9_deassert_reset(target_t *target);
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int arm7_9_reset_request_halt(target_t *target);
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int arm7_9_early_halt(target_t *target);
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int arm7_9_soft_reset_halt(struct target_s *target);
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int arm7_9_prepare_reset_halt(struct target_s *target);
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int arm7_9_halt(target_t *target);
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int arm7_9_full_context(target_t *target);
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int arm7_9_restore_context(target_t *target);
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int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
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int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
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int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
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int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
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int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum);
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int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank);
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int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, uint32_t entry_point, void *arch_info);
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int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
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int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
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int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
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void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc);
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void arm7_9_disable_eice_step(target_t *target);
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int arm7_9_execute_sys_speed(struct target_s *target);
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int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
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int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
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#endif /* ARM7_9_COMMON_H */
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