8c290412d2
- ST STM32x flash support added - cleaned up armv7m and cortex-m3 support, removed luminary specific code - cortex-m3 16bit read/write added (required for STM32x flash programming) git-svn-id: svn://svn.berlios.de/openocd/trunk@177 b42882b7-edfa-0310-969c-e2dbd0fdcd60
132 lines
5.2 KiB
C
132 lines
5.2 KiB
C
/***************************************************************************
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef CORTEX_SWJDP_H
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#define CORTEX_SWJDP_H
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#include "target.h"
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#include "register.h"
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#include "arm_jtag.h"
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#define SWJDP_IR_DPACC 0xA
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#define SWJDP_IR_APACC 0xB
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#define DPAP_WRITE 0
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#define DPAP_READ 1
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#define DP_ZERO 0
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#define DP_CTRL_STAT 0x4
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#define DP_SELECT 0x8
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#define DP_RDBUFF 0xC
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#define CORUNDETECT (1<<0)
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#define SSTICKYORUN (1<<1)
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#define SSTICKYERR (1<<5)
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#define CDBGRSTREQ (1<<26)
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#define CDBGRSTACK (1<<27)
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#define CDBGPWRUPREQ (1<<28)
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#define CDBGPWRUPACK (1<<29)
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#define CSYSPWRUPREQ (1<<30)
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#define CSYSPWRUPACK (1<<31)
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#define AHBAP_CSW 0x00
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#define AHBAP_TAR 0x04
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#define AHBAP_DRW 0x0C
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#define AHBAP_BD0 0x10
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#define AHBAP_BD1 0x14
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#define AHBAP_BD2 0x18
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#define AHBAP_BD3 0x1C
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#define AHBAP_DBGROMA 0xF8
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#define AHBAP_IDR 0xFC
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#define CSW_8BIT 0
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#define CSW_16BIT 1
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#define CSW_32BIT 2
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#define CSW_ADDRINC_MASK (3<<4)
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#define CSW_ADDRINC_OFF 0
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#define CSW_ADDRINC_SINGLE (1<<4)
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#define CSW_ADDRINC_PACKED (2<<4)
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#define CSW_HPROT (1<<25)
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#define CSW_MASTER_DEBUG (1<<29)
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#define CSW_DBGSWENABLE (1<<31)
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/* transaction mode */
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#define TRANS_MODE_NONE 0
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/* Transaction waits for previous to complete */
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#define TRANS_MODE_ATOMIC 1
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/* Freerunning transactions with delays and overrun checking */
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#define TRANS_MODE_COMPOSITE 2
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typedef struct swjdp_reg_s
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{
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int addr;
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arm_jtag_t *jtag_info;
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} swjdp_reg_t;
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typedef struct swjdp_common_s
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{
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arm_jtag_t *jtag_info;
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/* Control config */
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u32 dp_ctrl_stat;
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/* Register select cache */
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u32 dp_select_value;
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u32 ap_csw_value;
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u32 ap_tar_value;
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u8 prev_ack;
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/* information about current pending SWjDP-AHBAP transaction */
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u8 trans_mode;
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u8 trans_rw;
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u8 ack;
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u32 *trans_value;
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} swjdp_common_t;
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/* Internal functions used in the module, partial transactions, use with caution */
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extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
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//extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
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extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
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//extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
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extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
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extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
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/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
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extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
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extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
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extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
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/* External interface, complete atomic operations */
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/* Host endian word transfer of single memory and system registers */
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extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
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extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
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/* Target endian (u8*) buffer transfers of blocks of memory and system registers */
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extern int ahbap_read_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
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extern int ahbap_write_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
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/* Host endian word transfers of processor core registers */
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extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
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extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
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extern int ahbap_read_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
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extern int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
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extern int ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
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extern int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
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/* Initialisation of the debug system, power domains and registers */
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extern int ahbap_debugport_init(swjdp_common_t *swjdp);
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#endif
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