ba71e8c521
for - pio - pmc - rstc - wdt - sdramc - smc Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
22 lines
1.1 KiB
INI
22 lines
1.1 KiB
INI
set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register
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set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset
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set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset
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set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset
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set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password
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set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register
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set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status
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set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type
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set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)]
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set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)]
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set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)]
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set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)]
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set AT91_RSTC_RSTTYP_USER [expr (4 << 8)]
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set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level
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set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress
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set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register
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set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable
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set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable
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set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length
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