53b3d4dd53
Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
18 lines
362 B
INI
18 lines
362 B
INI
# Board from IAR KickStart Kit for LPC1768
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# See www.iar.com and also
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# http://www.olimex.com/dev/lpc-1766stk.html
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#
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source [find target/lpc1768.cfg]
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# The chip has just been reset.
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#
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$_TARGETNAME configure -event reset-init {
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# FIXME update the core clock to run at 100 MHz;
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# and update JTAG clocking similarly; then
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# make CCLK match,
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flash probe 0
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}
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