openocd/tcl/board/vd_a53x2_jtag.cfg
Jacek Wuwer f998a2aaf1 Cadence virtual debug interface (vdebug) integration
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14 15:12:10 +00:00

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759 B
INI

# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# Arm Cortex A53x2 through JTAG
source [find interface/vdebug.cfg]
set _CORES 2
set _CHIPNAME a53
set _MEMSTART 0x00000000
set _MEMSIZE 0x1000000
set _CPUTAPID 0x5ba00477
# vdebug select transport
#transport select jtag
# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 50000
adapter srst delay 5
# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
# DMA Memories to access backdoor (up to 4)
vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag arp_init-reset
source [find target/vd_aarch64.cfg]