53b3d4dd53
Fix some issues with the generic LPC1768 config file: - Handle the post-reset clock config: 4 MHz internal RC, no PLL. This affects flash and JTAG clocking. - Remove JTAG adapter config; they don't all support trst_and_srst - Remove the rest of the bogus "reset-init" event handler. - Allow explicit CCLK configuration, instead of assuming 12 MHz; some boards will use 100 Mhz (or the post-reset 4 MHz). - Simplify: rely on defaults for endianness and IR-Capture value - Update some comments too Build on those fixes to make a trivial config for the IAR LPC1768 kickstart board (by Olimex) start working. Also, add doxygen to the lpc2000 flash driver, primarily to note a configuration problem with driver: it wrongly assumes the core clock rate never changes. Configs that are safe for updating flash after "reset halt" will thus often be unsafe later ... e.g. for LPC1768, after switching to use PLL0 at 100 MHz. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
54 lines
1.7 KiB
INI
54 lines
1.7 KiB
INI
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc1768
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}
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK ] } {
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set _CCLK $CCLK
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} else {
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set _CCLK 4000
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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#delays on reset lines
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jtag_nsrst_delay 200
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jtag_ntrst_delay 200
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# LPC2000 & LPC1700 -> SRST causes TRST
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reset_config srst_pulls_trst
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# LPC1768 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
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# LPC1768 has 512kB of flash memory, managed by ROM code (including a
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# boot loader which verifies the flash exception table's checksum).
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# JTAG clock should be CCLK/6 (unless using adaptive clocking)
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# CCLK is 4 MHz after reset, and until board-specific code (like
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# a reset-init handler) speeds it up.
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jtag_rclk [ expr 4000 / 6 ]
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$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] }
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