The busy flag must be polled after each half-page write. At low clock speeds, no issue is observed when the poll is omitted, because the writes complete before the next write begins. But at high clock speeds the subsequent writes would overlap and cause the operation to fail. The status polls are done on the target for efficiency, since the half-pages are very small. Change-Id: Ia1e9b4a6a71930549b3d84a902744ce6e596301b Signed-off-by: Jimmy <nhminus@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5598 Tested-by: jenkins Reviewed-by: Jelle De Vleeschouwer Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
81 lines
2.9 KiB
ArmAsm
81 lines
2.9 KiB
ArmAsm
/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2011 Clement Burin des Roziers *
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* clement.burin-des-roziers@hikob.com *
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* *
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* Copyright (C) 2017 Armin van der Togt *
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* armin@otheruse.nl *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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***************************************************************************/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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/*
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Parameters
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r0 - destination address
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r1 - source address
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r2 - half pages
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r3 - bytes per half page
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r4 - flash base
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Variables
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r0 - destination write pointer
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r1 - source read pointer
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r2 - source limit address
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r3 - bytes per half page
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r4 - flash base
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r5 - pages left in current half page
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r6 - temporary r/w
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*/
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/* offsets of registers from flash reg base */
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#define STM32_FLASH_SR_OFFSET 0x18
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.thumb_func
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.global _start
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_start:
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// r2 = source + half pages * bytes per half page
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muls r2, r2, r3
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add r2, r1, r2
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// Go to compare
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b test_done
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write_half_page:
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// initialize pages left in current half page
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mov r5, r3
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write_word:
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// load word from address in r1 and increase r1 by 4
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ldmia r1!, {r6}
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// store word to address in r0 and increase r0 by 4
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stmia r0!, {r6}
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// check for end of half page
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subs r5, r5, #4
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bne write_word
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wait_busy:
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// read status register into r6, loop while bottom bit is set
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ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
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lsls r6, r6, #31
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bne wait_busy
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test_done:
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// compare r1 and r2, loop if not equal
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cmp r1, r2
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bne write_half_page
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// Set breakpoint to exit
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bkpt #0x00
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