705 lines
21 KiB
C
705 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* ESP Xtensa SMP target API for OpenOCD *
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* Copyright (C) 2020 Espressif Systems Ltd. Co *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "assert.h"
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#include <target/target.h>
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#include <target/target_type.h>
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#include <target/smp.h>
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#include "esp_xtensa_smp.h"
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/*
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Multiprocessor stuff common:
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The ESP Xtensa chip can have several cores in it, which can run in SMP-mode if an
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SMP-capable OS is running. The hardware has a few features which makes
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SMP debugging much easier.
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First of all, there's something called a 'break network', consisting of a
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BreakIn input and a BreakOut output on each CPU. The idea is that as soon
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as a CPU goes into debug mode for whatever reason, it'll signal that using
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its DebugOut pin. This signal is connected to the other CPU's DebugIn
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input, causing this CPU also to go into debugging mode. To resume execution
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when using only this break network, we will need to manually resume both
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CPUs.
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An alternative to this is the XOCDMode output and the RunStall (or DebugStall)
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input. When these are cross-connected, a CPU that goes into debug mode will
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halt execution entirely on the other CPU. Execution on the other CPU can be
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resumed by either the first CPU going out of debug mode, or the second CPU
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going into debug mode: the stall is temporarily lifted as long as the stalled
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CPU is in debug mode.
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A third, separate, signal is CrossTrigger. This is connected in the same way
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as the breakIn/breakOut network, but is for the TRAX (trace memory) feature;
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it does not affect OCD in any way.
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*/
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/*
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Multiprocessor stuff:
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The ESP Xtensa chip has several Xtensa cores inside, but represent themself to the OCD
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as one chip that works in multithreading mode under FreeRTOS OS.
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The core that initiate the stop condition will be defined as an active cpu.
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When one core stops, then other core will be stopped automatically by smpbreak.
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The core that initiates stop condition will be defined as an active core, and
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registers of this core will be transferred.
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*/
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#define ESP_XTENSA_SMP_EXAMINE_OTHER_CORES 5
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static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume);
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static inline struct esp_xtensa_smp_common *target_to_esp_xtensa_smp(struct target *target)
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{
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return container_of(target->arch_info, struct esp_xtensa_smp_common, esp_xtensa);
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}
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int esp_xtensa_smp_assert_reset(struct target *target)
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{
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return ERROR_OK;
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}
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int esp_xtensa_smp_deassert_reset(struct target *target)
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{
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LOG_TARGET_DEBUG(target, "begin");
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int ret = xtensa_deassert_reset(target);
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if (ret != ERROR_OK)
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return ret;
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/* in SMP mode when chip was running single-core app the other core can be left un-examined,
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because examination is done before SOC reset. But after SOC reset it is functional and should be handled.
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So try to examine un-examined core just after SOC reset */
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if (target->smp && !target_was_examined(target))
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ret = xtensa_examine(target);
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return ret;
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}
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int esp_xtensa_smp_soft_reset_halt(struct target *target)
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{
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int res;
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struct target_list *head;
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struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
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LOG_TARGET_DEBUG(target, "begin");
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/* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU
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and then call xtensa_assert_reset() for all cores */
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if (target->smp && target->coreid != 0)
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return ERROR_OK;
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/* Reset the SoC first */
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if (esp_xtensa_smp->chip_ops->reset) {
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res = esp_xtensa_smp->chip_ops->reset(target);
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if (res != ERROR_OK)
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return res;
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}
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if (!target->smp)
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return xtensa_assert_reset(target);
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foreach_smp_target(head, target->smp_targets) {
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res = xtensa_assert_reset(head->target);
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if (res != ERROR_OK)
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return res;
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}
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return ERROR_OK;
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}
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static struct target *get_halted_esp_xtensa_smp(struct target *target, int32_t coreid)
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{
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struct target_list *head;
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struct target *curr;
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foreach_smp_target(head, target->smp_targets) {
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curr = head->target;
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if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
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return curr;
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}
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return target;
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}
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int esp_xtensa_smp_poll(struct target *target)
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{
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enum target_state old_state = target->state;
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struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
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struct target_list *head;
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struct target *curr;
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bool other_core_resume_req = false;
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if (target->state == TARGET_HALTED && target->smp && target->gdb_service && !target->gdb_service->target) {
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target->gdb_service->target = get_halted_esp_xtensa_smp(target, target->gdb_service->core[1]);
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LOG_INFO("Switch GDB target to '%s'", target_name(target->gdb_service->target));
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if (esp_xtensa_smp->chip_ops->on_halt)
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esp_xtensa_smp->chip_ops->on_halt(target);
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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return ERROR_OK;
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}
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int ret = esp_xtensa_poll(target);
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if (ret != ERROR_OK)
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return ret;
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if (target->smp) {
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if (target->state == TARGET_RESET) {
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esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES;
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} else if (esp_xtensa_smp->examine_other_cores > 0 &&
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(target->state == TARGET_RUNNING || target->state == TARGET_HALTED)) {
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LOG_TARGET_DEBUG(target, "Check for unexamined cores after reset");
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bool all_examined = true;
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foreach_smp_target(head, target->smp_targets) {
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curr = head->target;
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if (curr == target)
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continue;
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if (!target_was_examined(curr)) {
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if (target_examine_one(curr) != ERROR_OK) {
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LOG_DEBUG("Failed to examine!");
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all_examined = false;
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}
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}
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}
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if (all_examined)
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esp_xtensa_smp->examine_other_cores = 0;
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else
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esp_xtensa_smp->examine_other_cores--;
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}
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}
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if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
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if (target->smp) {
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ret = esp_xtensa_smp_update_halt_gdb(target, &other_core_resume_req);
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if (ret != ERROR_OK)
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return ret;
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}
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/* Call any event callbacks that are applicable */
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if (old_state == TARGET_DEBUG_RUNNING) {
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
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} else {
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/* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
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if (target->smp && other_core_resume_req) {
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/* Resume xtensa_resume will handle BREAK instruction. */
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ret = target_resume(target, 1, 0, 1, 0);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to resume target");
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return ret;
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}
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return ERROR_OK;
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}
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if (esp_xtensa_smp->chip_ops->on_halt)
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esp_xtensa_smp->chip_ops->on_halt(target);
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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}
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return ERROR_OK;
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}
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static int esp_xtensa_smp_update_halt_gdb(struct target *target, bool *need_resume)
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{
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struct esp_xtensa_smp_common *esp_xtensa_smp;
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struct target *gdb_target = NULL;
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struct target_list *head;
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struct target *curr;
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int ret = ERROR_OK;
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*need_resume = false;
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if (target->gdb_service && target->gdb_service->target)
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LOG_DEBUG("GDB target '%s'", target_name(target->gdb_service->target));
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if (target->gdb_service && target->gdb_service->core[0] == -1) {
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target->gdb_service->target = target;
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target->gdb_service->core[0] = target->coreid;
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LOG_INFO("Set GDB target to '%s'", target_name(target));
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}
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if (target->gdb_service)
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gdb_target = target->gdb_service->target;
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/* due to smpbreak config other cores can also go to HALTED state */
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foreach_smp_target(head, target->smp_targets) {
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curr = head->target;
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LOG_DEBUG("Check target '%s'", target_name(curr));
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/* skip calling context */
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if (curr == target)
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continue;
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if (!target_was_examined(curr)) {
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curr->state = TARGET_HALTED;
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continue;
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}
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/* skip targets that were already halted */
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if (curr->state == TARGET_HALTED)
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continue;
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/* Skip gdb_target; it alerts GDB so has to be polled as last one */
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if (curr == gdb_target)
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continue;
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LOG_DEBUG("Poll target '%s'", target_name(curr));
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esp_xtensa_smp = target_to_esp_xtensa_smp(curr);
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/* avoid auto-resume after syscall, it will be done later */
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esp_xtensa_smp->other_core_does_resume = true;
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/* avoid recursion in esp_xtensa_smp_poll() */
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curr->smp = 0;
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if (esp_xtensa_smp->chip_ops->poll)
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ret = esp_xtensa_smp->chip_ops->poll(curr);
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else
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ret = esp_xtensa_smp_poll(curr);
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curr->smp = 1;
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if (ret != ERROR_OK)
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return ret;
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esp_xtensa_smp->other_core_does_resume = false;
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}
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/* after all targets were updated, poll the gdb serving target */
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if (gdb_target && gdb_target != target) {
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esp_xtensa_smp = target_to_esp_xtensa_smp(gdb_target);
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if (esp_xtensa_smp->chip_ops->poll)
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ret = esp_xtensa_smp->chip_ops->poll(gdb_target);
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else
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ret = esp_xtensa_smp_poll(gdb_target);
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}
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LOG_DEBUG("exit");
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return ret;
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}
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static inline int esp_xtensa_smp_smpbreak_disable(struct target *target, uint32_t *smp_break)
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{
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int res = xtensa_smpbreak_get(target, smp_break);
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if (res != ERROR_OK)
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return res;
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return xtensa_smpbreak_set(target, 0);
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}
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static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_t smp_break)
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{
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return xtensa_smpbreak_set(target, smp_break);
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}
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static int esp_xtensa_smp_resume_cores(struct target *target,
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int handle_breakpoints,
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int debug_execution)
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{
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struct target_list *head;
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struct target *curr;
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LOG_TARGET_DEBUG(target, "begin");
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foreach_smp_target(head, target->smp_targets) {
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curr = head->target;
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/* in single-core mode disabled core cannot be examined, but need to be resumed too*/
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if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) {
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/* resume current address, not in SMP mode */
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curr->smp = 0;
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int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution);
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curr->smp = 1;
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if (res != ERROR_OK)
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return res;
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}
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}
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return ERROR_OK;
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}
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int esp_xtensa_smp_resume(struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints,
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int debug_execution)
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{
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int res;
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uint32_t smp_break;
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xtensa_smpbreak_get(target, &smp_break);
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LOG_TARGET_DEBUG(target, "smp_break=0x%" PRIx32, smp_break);
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/* dummy resume for smp toggle in order to reduce gdb impact */
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if ((target->smp) && (target->gdb_service) && (target->gdb_service->core[1] != -1)) {
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/* simulate a start and halt of target */
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target->gdb_service->target = NULL;
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target->gdb_service->core[0] = target->gdb_service->core[1];
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/* fake resume at next poll we play the target core[1], see poll*/
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LOG_TARGET_DEBUG(target, "Fake resume");
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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return ERROR_OK;
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}
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/* xtensa_prepare_resume() can step over breakpoint/watchpoint and generate signals on BreakInOut circuit for
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* other cores. So disconnect this core from BreakInOut circuit and do xtensa_prepare_resume(). */
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res = esp_xtensa_smp_smpbreak_disable(target, &smp_break);
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if (res != ERROR_OK)
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return res;
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res = xtensa_prepare_resume(target, current, address, handle_breakpoints, debug_execution);
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/* restore configured BreakInOut signals config */
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int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break);
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if (ret != ERROR_OK)
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return ret;
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if (res != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to prepare for resume!");
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return res;
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}
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if (target->smp) {
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if (target->gdb_service)
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target->gdb_service->core[0] = -1;
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res = esp_xtensa_smp_resume_cores(target, handle_breakpoints, debug_execution);
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if (res != ERROR_OK)
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return res;
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}
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res = xtensa_do_resume(target);
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if (res != ERROR_OK) {
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LOG_TARGET_ERROR(target, "Failed to resume!");
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return res;
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}
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target->debug_reason = DBG_REASON_NOTHALTED;
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if (!debug_execution)
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target->state = TARGET_RUNNING;
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else
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target->state = TARGET_DEBUG_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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return ERROR_OK;
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}
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int esp_xtensa_smp_step(struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints)
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{
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int res;
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uint32_t smp_break = 0;
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struct esp_xtensa_smp_common *esp_xtensa_smp = target_to_esp_xtensa_smp(target);
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if (target->smp) {
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res = esp_xtensa_smp_smpbreak_disable(target, &smp_break);
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if (res != ERROR_OK)
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return res;
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}
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res = xtensa_step(target, current, address, handle_breakpoints);
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if (res == ERROR_OK) {
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if (esp_xtensa_smp->chip_ops->on_halt)
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esp_xtensa_smp->chip_ops->on_halt(target);
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target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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}
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if (target->smp) {
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int ret = esp_xtensa_smp_smpbreak_restore(target, smp_break);
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if (ret != ERROR_OK)
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return ret;
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}
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return res;
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}
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int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint)
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{
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int res = xtensa_watchpoint_add(target, watchpoint);
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if (res != ERROR_OK)
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return res;
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if (!target->smp)
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return ERROR_OK;
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struct target_list *head;
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foreach_smp_target(head, target->smp_targets) {
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struct target *curr = head->target;
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if (curr == target || !target_was_examined(curr))
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continue;
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/* Need to use high level API here because every target for core contains list of watchpoints.
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* GDB works with active core only, so we need to duplicate every watchpoint on other cores,
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* otherwise watchpoint_free() on active core can fail if WP has been initially added on another core. */
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curr->smp = 0;
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res = watchpoint_add(curr, watchpoint->address, watchpoint->length,
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watchpoint->rw, watchpoint->value, watchpoint->mask);
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curr->smp = 1;
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if (res != ERROR_OK)
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return res;
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}
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return ERROR_OK;
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}
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int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint)
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{
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int res = xtensa_watchpoint_remove(target, watchpoint);
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if (res != ERROR_OK)
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return res;
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if (!target->smp)
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return ERROR_OK;
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struct target_list *head;
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foreach_smp_target(head, target->smp_targets) {
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struct target *curr = head->target;
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if (curr == target)
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continue;
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/* see big comment in esp_xtensa_smp_watchpoint_add() */
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curr->smp = 0;
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watchpoint_remove(curr, watchpoint->address);
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curr->smp = 1;
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}
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return ERROR_OK;
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}
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int esp_xtensa_smp_init_arch_info(struct target *target,
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struct esp_xtensa_smp_common *esp_xtensa_smp,
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const struct xtensa_config *xtensa_cfg,
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struct xtensa_debug_module_config *dm_cfg,
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const struct esp_xtensa_smp_chip_ops *chip_ops)
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{
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int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
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if (ret != ERROR_OK)
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return ret;
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esp_xtensa_smp->chip_ops = chip_ops;
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esp_xtensa_smp->examine_other_cores = ESP_XTENSA_SMP_EXAMINE_OTHER_CORES;
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return ERROR_OK;
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}
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int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target)
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{
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return esp_xtensa_target_init(cmd_ctx, target);
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}
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COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
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{
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struct target *target = get_current_target(CMD_CTX);
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if (target->smp && CMD_ARGC > 0) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_smpbreak)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp && CMD_ARGC > 0) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, curr);
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do, target);
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_mask_interrupts)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp && CMD_ARGC > 0) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_enable)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp && CMD_ARGC > 0) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
LOG_INFO("CPU%d:", curr->coreid);
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestart)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestop)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do,
|
|
target_to_xtensa(curr));
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do,
|
|
target_to_xtensa(target));
|
|
}
|
|
|
|
COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
if (target->smp) {
|
|
struct target_list *head;
|
|
struct target *curr;
|
|
int32_t cores_max_id = 0;
|
|
/* assume that core IDs are assigned to SMP targets sequentially: 0,1,2... */
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
if (cores_max_id < curr->coreid)
|
|
cores_max_id = curr->coreid;
|
|
}
|
|
if (CMD_ARGC < ((uint32_t)cores_max_id + 1)) {
|
|
command_print(CMD,
|
|
"Need %d filenames to dump to as output!",
|
|
cores_max_id + 1);
|
|
return ERROR_FAIL;
|
|
}
|
|
foreach_smp_target(head, target->smp_targets) {
|
|
curr = head->target;
|
|
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do,
|
|
target_to_xtensa(curr), CMD_ARGV[curr->coreid]);
|
|
if (ret != ERROR_OK)
|
|
return ret;
|
|
}
|
|
return ERROR_OK;
|
|
}
|
|
return CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do,
|
|
target_to_xtensa(target), CMD_ARGV[0]);
|
|
}
|
|
|
|
const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = {
|
|
{
|
|
.name = "set_permissive",
|
|
.handler = esp_xtensa_smp_cmd_permissive_mode,
|
|
.mode = COMMAND_ANY,
|
|
.help = "When set to 1, enable Xtensa permissive mode (less client-side checks)",
|
|
.usage = "[0|1]",
|
|
},
|
|
{
|
|
.name = "maskisr",
|
|
.handler = esp_xtensa_smp_cmd_mask_interrupts,
|
|
.mode = COMMAND_ANY,
|
|
.help = "mask Xtensa interrupts at step",
|
|
.usage = "['on'|'off']",
|
|
},
|
|
{
|
|
.name = "smpbreak",
|
|
.handler = esp_xtensa_smp_cmd_smpbreak,
|
|
.mode = COMMAND_ANY,
|
|
.help = "Set the way the CPU chains OCD breaks",
|
|
.usage =
|
|
"[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]",
|
|
},
|
|
{
|
|
.name = "perfmon_enable",
|
|
.handler = esp_xtensa_smp_cmd_perfmon_enable,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Enable and start performance counter",
|
|
.usage = "<counter_id> <select> [mask] [kernelcnt] [tracelevel]",
|
|
},
|
|
{
|
|
.name = "perfmon_dump",
|
|
.handler = esp_xtensa_smp_cmd_perfmon_dump,
|
|
.mode = COMMAND_EXEC,
|
|
.help =
|
|
"Dump performance counter value. If no argument specified, dumps all counters.",
|
|
.usage = "[counter_id]",
|
|
},
|
|
{
|
|
.name = "tracestart",
|
|
.handler = esp_xtensa_smp_cmd_tracestart,
|
|
.mode = COMMAND_EXEC,
|
|
.help =
|
|
"Tracing: Set up and start a trace. Optionally set stop trigger address and amount of data captured after.",
|
|
.usage = "[pc <pcval>/[maskbitcount]] [after <n> [ins|words]]",
|
|
},
|
|
{
|
|
.name = "tracestop",
|
|
.handler = esp_xtensa_smp_cmd_tracestop,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Tracing: Stop current trace as started by the tracestart command",
|
|
.usage = "",
|
|
},
|
|
{
|
|
.name = "tracedump",
|
|
.handler = esp_xtensa_smp_cmd_tracedump,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Tracing: Dump trace memory to a files. One file per core.",
|
|
.usage = "<outfile1> <outfile2>",
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration esp_xtensa_smp_command_handlers[] = {
|
|
{
|
|
.name = "xtensa",
|
|
.usage = "",
|
|
.chain = esp_xtensa_smp_xtensa_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|