268 lines
5.8 KiB
C
268 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Generic Xtensa target API for OpenOCD *
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* Copyright (C) 2016-2019 Espressif Systems Ltd. *
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* Author: Angus Gratton gus@projectgus.com *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_XTENSA_REGS_H
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#define OPENOCD_TARGET_XTENSA_REGS_H
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struct reg_arch_type;
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enum xtensa_reg_id {
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XT_REG_IDX_PC = 0,
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XT_REG_IDX_AR0,
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XT_REG_IDX_AR1,
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XT_REG_IDX_AR2,
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XT_REG_IDX_AR3,
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XT_REG_IDX_AR4,
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XT_REG_IDX_AR5,
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XT_REG_IDX_AR6,
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XT_REG_IDX_AR7,
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XT_REG_IDX_AR8,
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XT_REG_IDX_AR9,
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XT_REG_IDX_AR10,
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XT_REG_IDX_AR11,
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XT_REG_IDX_AR12,
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XT_REG_IDX_AR13,
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XT_REG_IDX_AR14,
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XT_REG_IDX_AR15,
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XT_REG_IDX_AR16,
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XT_REG_IDX_AR17,
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XT_REG_IDX_AR18,
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XT_REG_IDX_AR19,
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XT_REG_IDX_AR20,
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XT_REG_IDX_AR21,
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XT_REG_IDX_AR22,
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XT_REG_IDX_AR23,
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XT_REG_IDX_AR24,
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XT_REG_IDX_AR25,
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XT_REG_IDX_AR26,
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XT_REG_IDX_AR27,
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XT_REG_IDX_AR28,
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XT_REG_IDX_AR29,
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XT_REG_IDX_AR30,
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XT_REG_IDX_AR31,
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XT_REG_IDX_AR32,
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XT_REG_IDX_AR33,
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XT_REG_IDX_AR34,
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XT_REG_IDX_AR35,
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XT_REG_IDX_AR36,
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XT_REG_IDX_AR37,
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XT_REG_IDX_AR38,
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XT_REG_IDX_AR39,
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XT_REG_IDX_AR40,
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XT_REG_IDX_AR41,
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XT_REG_IDX_AR42,
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XT_REG_IDX_AR43,
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XT_REG_IDX_AR44,
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XT_REG_IDX_AR45,
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XT_REG_IDX_AR46,
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XT_REG_IDX_AR47,
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XT_REG_IDX_AR48,
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XT_REG_IDX_AR49,
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XT_REG_IDX_AR50,
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XT_REG_IDX_AR51,
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XT_REG_IDX_AR52,
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XT_REG_IDX_AR53,
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XT_REG_IDX_AR54,
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XT_REG_IDX_AR55,
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XT_REG_IDX_AR56,
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XT_REG_IDX_AR57,
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XT_REG_IDX_AR58,
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XT_REG_IDX_AR59,
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XT_REG_IDX_AR60,
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XT_REG_IDX_AR61,
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XT_REG_IDX_AR62,
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XT_REG_IDX_AR63,
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XT_REG_IDX_LBEG,
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XT_REG_IDX_LEND,
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XT_REG_IDX_LCOUNT,
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XT_REG_IDX_SAR,
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XT_REG_IDX_WINDOWBASE,
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XT_REG_IDX_WINDOWSTART,
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XT_REG_IDX_CONFIGID0,
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XT_REG_IDX_CONFIGID1,
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XT_REG_IDX_PS,
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XT_REG_IDX_THREADPTR,
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XT_REG_IDX_BR,
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XT_REG_IDX_SCOMPARE1,
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XT_REG_IDX_ACCLO,
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XT_REG_IDX_ACCHI,
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XT_REG_IDX_M0,
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XT_REG_IDX_M1,
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XT_REG_IDX_M2,
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XT_REG_IDX_M3,
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XT_REG_IDX_F0,
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XT_REG_IDX_F1,
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XT_REG_IDX_F2,
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XT_REG_IDX_F3,
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XT_REG_IDX_F4,
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XT_REG_IDX_F5,
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XT_REG_IDX_F6,
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XT_REG_IDX_F7,
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XT_REG_IDX_F8,
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XT_REG_IDX_F9,
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XT_REG_IDX_F10,
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XT_REG_IDX_F11,
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XT_REG_IDX_F12,
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XT_REG_IDX_F13,
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XT_REG_IDX_F14,
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XT_REG_IDX_F15,
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XT_REG_IDX_FCR,
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XT_REG_IDX_FSR,
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XT_REG_IDX_MMID,
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XT_REG_IDX_IBREAKENABLE,
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XT_REG_IDX_MEMCTL,
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XT_REG_IDX_ATOMCTL,
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XT_REG_IDX_IBREAKA0,
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XT_REG_IDX_IBREAKA1,
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XT_REG_IDX_DBREAKA0,
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XT_REG_IDX_DBREAKA1,
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XT_REG_IDX_DBREAKC0,
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XT_REG_IDX_DBREAKC1,
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XT_REG_IDX_EPC1,
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XT_REG_IDX_EPC2,
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XT_REG_IDX_EPC3,
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XT_REG_IDX_EPC4,
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XT_REG_IDX_EPC5,
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XT_REG_IDX_EPC6,
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XT_REG_IDX_EPC7,
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XT_REG_IDX_DEPC,
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XT_REG_IDX_EPS2,
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XT_REG_IDX_EPS3,
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XT_REG_IDX_EPS4,
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XT_REG_IDX_EPS5,
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XT_REG_IDX_EPS6,
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XT_REG_IDX_EPS7,
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XT_REG_IDX_EXCSAVE1,
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XT_REG_IDX_EXCSAVE2,
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XT_REG_IDX_EXCSAVE3,
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XT_REG_IDX_EXCSAVE4,
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XT_REG_IDX_EXCSAVE5,
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XT_REG_IDX_EXCSAVE6,
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XT_REG_IDX_EXCSAVE7,
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XT_REG_IDX_CPENABLE,
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XT_REG_IDX_INTERRUPT,
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XT_REG_IDX_INTSET,
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XT_REG_IDX_INTCLEAR,
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XT_REG_IDX_INTENABLE,
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XT_REG_IDX_VECBASE,
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XT_REG_IDX_EXCCAUSE,
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XT_REG_IDX_DEBUGCAUSE,
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XT_REG_IDX_CCOUNT,
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XT_REG_IDX_PRID,
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XT_REG_IDX_ICOUNT,
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XT_REG_IDX_ICOUNTLEVEL,
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XT_REG_IDX_EXCVADDR,
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XT_REG_IDX_CCOMPARE0,
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XT_REG_IDX_CCOMPARE1,
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XT_REG_IDX_CCOMPARE2,
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XT_REG_IDX_MISC0,
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XT_REG_IDX_MISC1,
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XT_REG_IDX_MISC2,
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XT_REG_IDX_MISC3,
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XT_REG_IDX_LITBASE,
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XT_REG_IDX_PTEVADDR,
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XT_REG_IDX_RASID,
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XT_REG_IDX_ITLBCFG,
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XT_REG_IDX_DTLBCFG,
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XT_REG_IDX_MEPC,
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XT_REG_IDX_MEPS,
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XT_REG_IDX_MESAVE,
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XT_REG_IDX_MESR,
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XT_REG_IDX_MECR,
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XT_REG_IDX_MEVADDR,
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XT_REG_IDX_A0,
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XT_REG_IDX_A1,
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XT_REG_IDX_A2,
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XT_REG_IDX_A3,
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XT_REG_IDX_A4,
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XT_REG_IDX_A5,
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XT_REG_IDX_A6,
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XT_REG_IDX_A7,
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XT_REG_IDX_A8,
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XT_REG_IDX_A9,
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XT_REG_IDX_A10,
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XT_REG_IDX_A11,
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XT_REG_IDX_A12,
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XT_REG_IDX_A13,
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XT_REG_IDX_A14,
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XT_REG_IDX_A15,
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XT_REG_IDX_PWRCTL,
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XT_REG_IDX_PWRSTAT,
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XT_REG_IDX_ERISTAT,
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XT_REG_IDX_CS_ITCTRL,
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XT_REG_IDX_CS_CLAIMSET,
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XT_REG_IDX_CS_CLAIMCLR,
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XT_REG_IDX_CS_LOCKACCESS,
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XT_REG_IDX_CS_LOCKSTATUS,
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XT_REG_IDX_CS_AUTHSTATUS,
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XT_REG_IDX_FAULT_INFO,
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XT_REG_IDX_TRAX_ID,
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XT_REG_IDX_TRAX_CTRL,
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XT_REG_IDX_TRAX_STAT,
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XT_REG_IDX_TRAX_DATA,
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XT_REG_IDX_TRAX_ADDR,
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XT_REG_IDX_TRAX_PCTRIGGER,
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XT_REG_IDX_TRAX_PCMATCH,
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XT_REG_IDX_TRAX_DELAY,
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XT_REG_IDX_TRAX_MEMSTART,
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XT_REG_IDX_TRAX_MEMEND,
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XT_REG_IDX_PMG,
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XT_REG_IDX_PMPC,
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XT_REG_IDX_PM0,
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XT_REG_IDX_PM1,
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XT_REG_IDX_PMCTRL0,
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XT_REG_IDX_PMCTRL1,
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XT_REG_IDX_PMSTAT0,
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XT_REG_IDX_PMSTAT1,
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XT_REG_IDX_OCD_ID,
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XT_REG_IDX_OCD_DCRCLR,
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XT_REG_IDX_OCD_DCRSET,
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XT_REG_IDX_OCD_DSR,
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XT_REG_IDX_OCD_DDR,
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XT_NUM_REGS,
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/* chip-specific user registers go after ISA-defined ones */
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XT_USR_REG_START = XT_NUM_REGS
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};
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typedef uint32_t xtensa_reg_val_t;
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enum xtensa_reg_type {
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XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */
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XT_REG_USER = 1, /* User register, needs RUR to read */
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XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */
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XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */
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XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window
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*index */
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XT_REG_FR = 5, /* Floating-point register */
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};
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enum xtensa_reg_flags {
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XT_REGF_NOREAD = 0x01, /* Register is write-only */
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XT_REGF_COPROC0 = 0x02 /* Can't be read if coproc0 isn't enabled */
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};
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struct xtensa_reg_desc {
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const char *name;
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unsigned int reg_num; /* ISA register num (meaning depends on register type) */
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enum xtensa_reg_type type;
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enum xtensa_reg_flags flags;
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};
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struct xtensa_user_reg_desc {
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const char *name;
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/* ISA register num (meaning depends on register type) */
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unsigned int reg_num;
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enum xtensa_reg_flags flags;
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uint32_t size;
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const struct reg_arch_type *type;
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};
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extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
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#endif /* OPENOCD_TARGET_XTENSA_REGS_H */
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