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9ee9bdd2f9
openocd/src/target/Makefile.am
Evgeniy Didin 9ee9bdd2f9 Introduce ARCv2 architecture related code 
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.

Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
        Mem leak in functions:
                arc_jtag_read_memory,arc_jtag_read_memory,
                arc_jtag_write_registers, arc_jtag_read_registers,
                jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
                arc_build_reg_cache, arc_mem_read.
        Dead code in "arc_mem_read";
        In arc_save_context, arc_restore_context correct arguments
        in"memset" calls.
        In "build_bcr_reg_cache", "arc_build_reg_cache" check
        if list is not empty.

29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers

22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
        * add irq_state field in arc_common
        * fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup

30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
	Valgrind shows no memory leaks.
-Inroduced arch description in arc.c

01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
	and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
	to separate functions.

19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
 to reduce amount of memory allocations calls
 and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
 reg_data_type_bitfield object and char[] name. Reduces
 memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
 argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
 during regiter r/w.

24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup

Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
2020-02-27 06:46:51 +00:00

261 lines
4.5 KiB
Makefile
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if OOCD_TRACE
OOCD_TRACE_FILES = %D%/oocd_trace.c
else
OOCD_TRACE_FILES =
endif
%C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
%D%/riscv/libriscv.la
STARTUP_TCL_SRCS += %D%/startup.tcl
noinst_LTLIBRARIES += %D%/libtarget.la
%C%_libtarget_la_SOURCES = \
$(TARGET_CORE_SRC) \
$(ARM_DEBUG_SRC) \
$(ARMV4_5_SRC) \
$(ARMV6_SRC) \
$(ARMV7_SRC) \
$(ARM_MISC_SRC) \
$(AVR32_SRC) \
$(MIPS32_SRC) \
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(ESIRISC_SRC) \
$(ARC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
%D%/dsp5680xx.c \
%D%/hla_target.c
if TARGET64
%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
endif
TARGET_CORE_SRC = \
%D%/algorithm.c \
%D%/register.c \
%D%/image.c \
%D%/breakpoints.c \
%D%/target.c \
%D%/target_request.c \
%D%/testee.c \
%D%/semihosting_common.c \
%D%/smp.c
ARMV4_5_SRC = \
%D%/armv4_5.c \
%D%/armv4_5_mmu.c \
%D%/armv4_5_cache.c \
$(ARM7_9_SRC)
ARM7_9_SRC = \
%D%/arm7_9_common.c \
%D%/arm7tdmi.c \
%D%/arm720t.c \
%D%/arm9tdmi.c \
%D%/arm920t.c \
%D%/arm966e.c \
%D%/arm946e.c \
%D%/arm926ejs.c \
%D%/feroceon.c
ARM_MISC_SRC = \
%D%/fa526.c \
%D%/xscale.c
ARMV6_SRC = \
%D%/arm11.c \
%D%/arm11_dbgtap.c
ARMV7_SRC = \
%D%/armv7m.c \
%D%/armv7m_trace.c \
%D%/cortex_m.c \
%D%/armv7a.c \
%D%/armv7a_mmu.c \
%D%/cortex_a.c \
%D%/ls1_sap.c \
%D%/mem_ap.c
ARMV8_SRC = \
%D%/armv8_dpm.c \
%D%/armv8_opcodes.c \
%D%/aarch64.c \
%D%/armv8.c \
%D%/armv8_cache.c
ARM_DEBUG_SRC = \
%D%/arm_dpm.c \
%D%/arm_jtag.c \
%D%/arm_disassembler.c \
%D%/arm_simulator.c \
%D%/arm_semihosting.c \
%D%/arm_adi_v5.c \
%D%/arm_dap.c \
%D%/armv7a_cache.c \
%D%/armv7a_cache_l2x.c \
%D%/adi_v5_dapdirect.c \
%D%/adi_v5_jtag.c \
%D%/adi_v5_swd.c \
%D%/embeddedice.c \
%D%/trace.c \
%D%/etb.c \
%D%/etm.c \
$(OOCD_TRACE_FILES) \
%D%/etm_dummy.c \
%D%/arm_cti.c
AVR32_SRC = \
%D%/avr32_ap7k.c \
%D%/avr32_jtag.c \
%D%/avr32_mem.c \
%D%/avr32_regs.c
MIPS32_SRC = \
%D%/mips32.c \
%D%/mips_m4k.c \
%D%/mips32_pracc.c \
%D%/mips32_dmaacc.c \
%D%/mips_ejtag.c
MIPS64_SRC = \
%D%/mips64.c \
%D%/mips32_pracc.c \
%D%/mips64_pracc.c \
%D%/mips_mips64.c \
%D%/trace.c \
%D%/mips_ejtag.c
NDS32_SRC = \
%D%/nds32.c \
%D%/nds32_reg.c \
%D%/nds32_cmd.c \
%D%/nds32_disassembler.c \
%D%/nds32_tlb.c \
%D%/nds32_v2.c \
%D%/nds32_v3_common.c \
%D%/nds32_v3.c \
%D%/nds32_v3m.c \
%D%/nds32_aice.c
STM8_SRC = \
%D%/stm8.c
INTEL_IA32_SRC = \
%D%/quark_x10xx.c \
%D%/quark_d20xx.c \
%D%/lakemont.c \
%D%/x86_32_common.c
ESIRISC_SRC = \
%D%/esirisc.c \
%D%/esirisc_jtag.c \
%D%/esirisc_trace.c
ARC_SRC = \
%D%/arc.c \
%D%/arc_cmd.c \
%D%/arc_jtag.c \
%D%/arc_mem.c
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
%D%/arm_dpm.h \
%D%/arm_jtag.h \
%D%/arm_adi_v5.h \
%D%/armv7a_cache.h \
%D%/armv7a_cache_l2x.h \
%D%/armv7a_mmu.h \
%D%/arm_disassembler.h \
%D%/arm_opcodes.h \
%D%/arm_simulator.h \
%D%/arm_semihosting.h \
%D%/arm7_9_common.h \
%D%/arm7tdmi.h \
%D%/arm720t.h \
%D%/arm9tdmi.h \
%D%/arm920t.h \
%D%/arm926ejs.h \
%D%/arm966e.h \
%D%/arm946e.h \
%D%/arm11.h \
%D%/arm11_dbgtap.h \
%D%/armv4_5.h \
%D%/armv4_5_mmu.h \
%D%/armv4_5_cache.h \
%D%/armv7a.h \
%D%/armv7m.h \
%D%/armv7m_trace.h \
%D%/armv8.h \
%D%/armv8_dpm.h \
%D%/armv8_opcodes.h \
%D%/armv8_cache.h \
%D%/avrt.h \
%D%/dsp563xx.h \
%D%/dsp563xx_once.h \
%D%/dsp5680xx.h \
%D%/breakpoints.h \
%D%/cortex_m.h \
%D%/cortex_a.h \
%D%/aarch64.h \
%D%/embeddedice.h \
%D%/etb.h \
%D%/etm.h \
%D%/etm_dummy.h \
%D%/image.h \
%D%/mips32.h \
%D%/mips64.h \
%D%/mips_m4k.h \
%D%/mips_mips64.h \
%D%/mips_ejtag.h \
%D%/mips32_pracc.h \
%D%/mips32_dmaacc.h \
%D%/mips64_pracc.h \
%D%/oocd_trace.h \
%D%/register.h \
%D%/target.h \
%D%/target_type.h \
%D%/trace.h \
%D%/target_request.h \
%D%/trace.h \
%D%/xscale.h \
%D%/smp.h \
%D%/avr32_ap7k.h \
%D%/avr32_jtag.h \
%D%/avr32_mem.h \
%D%/avr32_regs.h \
%D%/nds32.h \
%D%/nds32_cmd.h \
%D%/nds32_disassembler.h \
%D%/nds32_edm.h \
%D%/nds32_insn.h \
%D%/nds32_reg.h \
%D%/nds32_tlb.h \
%D%/nds32_v2.h \
%D%/nds32_v3_common.h \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
%D%/semihosting_common.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/arm_cti.h \
%D%/esirisc.h \
%D%/esirisc_jtag.h \
%D%/esirisc_regs.h \
%D%/esirisc_trace.h \
%D%/arc.h \
%D%/arc_cmd.h \
%D%/arc_jtag.h \
%D%/arc_mem.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am
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