eb6c880ddc
Move the symbols for these bits from "armv7a.h" to "arm_dpm.h", where they can be seen and used not just by Cortex-A but also by the ARM11 (armv6) code. Change them from bit numbers to bit masks ... this matches the usage in ARM11 code, and also makes it easier to read. Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's enabling ITR functionality, not external interrupts, so this changes the name to be less misleading. (There *IS* a bit affecting interrupts, and this isn't it.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
141 lines
4.0 KiB
C
141 lines
4.0 KiB
C
/***************************************************************************
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* Copyright (C) 2009 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef ARMV7A_H
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#define ARMV7A_H
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#include <target/arm_adi_v5.h>
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#include <target/armv4_5.h>
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#include <target/armv4_5_mmu.h>
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#include <target/armv4_5_cache.h>
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#include <target/arm_dpm.h>
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enum
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{
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ARM_PC = 15,
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ARM_CPSR = 16
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}
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;
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#define ARMV7_COMMON_MAGIC 0x0A450999
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/* VA to PA translation operations opc2 values*/
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#define V2PCWPR 0
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#define V2PCWPW 1
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#define V2PCWUR 2
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#define V2PCWUW 3
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#define V2POWPR 4
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#define V2POWPW 5
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#define V2POWUR 6
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#define V2POWUW 7
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struct armv7a_common
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{
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struct arm armv4_5_common;
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int common_magic;
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struct reg_cache *core_cache;
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/* arm adp debug port */
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struct swjdp_common swjdp_info;
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/* Core Debug Unit */
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struct arm_dpm dpm;
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uint32_t debug_base;
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uint8_t debug_ap;
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uint8_t memory_ap;
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/* Cache and Memory Management Unit */
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struct armv4_5_mmu_common armv4_5_mmu;
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int (*examine_debug_reason)(struct target *target);
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void (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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void (*post_restore_context)(struct target *target);
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};
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static inline struct armv7a_common *
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target_to_armv7a(struct target *target)
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{
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return container_of(target->arch_info, struct armv7a_common,
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armv4_5_common);
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}
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/* register offsets from armv7a.debug_base */
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/* See ARMv7a arch spec section C10.2 */
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#define CPUDBG_DIDR 0x000
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/* See ARMv7a arch spec section C10.3 */
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#define CPUDBG_WFAR 0x018
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/* PCSR at 0x084 -or- 0x0a0 -or- both ... based on flags in DIDR */
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#define CPUDBG_DSCR 0x088
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#define CPUDBG_DRCR 0x090
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#define CPUDBG_PRCR 0x310
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#define CPUDBG_PRSR 0x314
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/* See ARMv7a arch spec section C10.4 */
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#define CPUDBG_DTRRX 0x080
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#define CPUDBG_ITR 0x084
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#define CPUDBG_DTRTX 0x08c
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/* See ARMv7a arch spec section C10.5 */
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#define CPUDBG_BVR_BASE 0x100
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#define CPUDBG_BCR_BASE 0x140
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#define CPUDBG_WVR_BASE 0x180
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#define CPUDBG_WCR_BASE 0x1C0
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#define CPUDBG_VCR 0x01C
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/* See ARMv7a arch spec section C10.6 */
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#define CPUDBG_OSLAR 0x300
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#define CPUDBG_OSLSR 0x304
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#define CPUDBG_OSSRR 0x308
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#define CPUDBG_ECR 0x024
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/* See ARMv7a arch spec section C10.7 */
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#define CPUDBG_DSCCR 0x028
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/* See ARMv7a arch spec section C10.8 */
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#define CPUDBG_AUTHSTATUS 0xFB8
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struct armv7a_algorithm
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{
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int common_magic;
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enum armv4_5_mode core_mode;
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enum armv4_5_state core_state;
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};
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struct armv7a_core_reg
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{
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int num;
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enum armv4_5_mode mode;
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struct target *target;
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struct armv7a_common *armv7a_common;
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};
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int armv7a_arch_state(struct target *target);
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struct reg_cache *armv7a_build_reg_cache(struct target *target,
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struct armv7a_common *armv7a_common);
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int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
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extern const struct command_registration armv7a_command_handlers[];
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#endif /* ARMV4_5_H */
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