44d6a531f7
ARM9 cores with an ETB will have a matching ETM. Hook them both up by default. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
54 lines
1.4 KiB
INI
54 lines
1.4 KiB
INI
# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3"
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# SRST pulls TRST
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#
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# Without setting these options correctly you'll see all sorts
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# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset
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# failing, etc.
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reset_config trst_and_srst srst_pulls_trst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imx27
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Note above there are 2 taps
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# trace buffer
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if { [info exists ETBTAPID ] } {
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set _ETBTAPID $ETBTAPID
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} else {
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set _ETBTAPID 0x1b900f0f
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}
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jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
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# The CPU tap
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x07926121
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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# Create the GDB Target.
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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# REVISIT what operating environment sets up this virtual address mapping?
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$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
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-work-area-size 0x8000 -work-area-backup 1
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# Internal to the chip, there is 45K of SRAM
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#
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arm7_9 dcc_downloads enable
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# trace setup
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etm config $_TARGETNAME 16 normal full etb
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etb config $_TARGETNAME $_CHIPNAME.etb
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