d25355473d
Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
62 lines
797 B
Makefile
62 lines
797 B
Makefile
include $(top_srcdir)/common.mk
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noinst_LTLIBRARIES = libocdflashnor.la
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libocdflashnor_la_SOURCES = \
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core.c \
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tcl.c \
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$(NOR_DRIVERS) \
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drivers.c
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NOR_DRIVERS = \
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aduc702x.c \
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at91sam4.c \
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at91sam4l.c \
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at91samd.c \
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at91sam3.c \
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at91sam7.c \
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avrf.c \
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cfi.c \
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efm32.c \
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em357.c \
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faux.c \
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jtagspi.c \
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lpc2000.c \
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lpc288x.c \
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lpc2900.c \
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lpcspifi.c \
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mdr.c \
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non_cfi.c \
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ocl.c \
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pic32mx.c \
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spi.c \
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stmsmi.c \
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stellaris.c \
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stm32f1x.c \
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stm32f2x.c \
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stm32lx.c \
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str7x.c \
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str9x.c \
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str9xpec.c \
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tms470.c \
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virtual.c \
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fm3.c \
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dsp5680xx_flash.c \
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kinetis.c \
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mini51.c \
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nuc1x.c \
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nrf51.c \
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mrvlqspi.c \
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psoc4.c \
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sim3x.c
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noinst_HEADERS = \
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core.h \
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cfi.h \
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driver.h \
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imp.h \
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non_cfi.h \
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ocl.h \
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spi.h
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MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
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